Programmable RF Digital Filter Using Parallel Convolution and Serialization
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Solution Overview
Problem
Conventional digital filters face challenges in processing data at higher carrier frequencies, as the short clock period does not allow sufficient time for digital processing, making it difficult to implement effectively at frequencies such as 6 GHz and above.
Innovation Solution
A digital filter design that includes a processing circuit with parallel processing circuits operating at a lower clock frequency, allowing for sufficient time to perform mathematical operations, and a serializer that outputs data at a radio frequency (RF) by using a clock generator to provide a second clock signal that is an integer multiple of the first, enabling data to be modulated as a carrier frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital filters process data at higher carrier frequencies, then the data rate increases, but the clock period becomes too short to allow sufficient time for digital processing operations
Solution Approach 1:
The filter is divided into multiple parallel processing circuits (first, second, third, and fourth parallel processing circuits) that simultaneously process different portions of the input signal. This segmentation allows the overall processing to be completed within the short clock period at higher carrier frequencies, as each segment processes a fraction of the total computation required.
2Loss of time
If parallel processing circuits are used to perform mathematical operations at lower clock frequency, then processing time increases, but the output data rate must still match the high RF frequency
Solution Approach 1:
The patent transitions from time-domain parallelism to frequency-domain parallelism by using multiple parallel processing circuits that operate simultaneously. Each circuit processes a different portion of the impulse response, and their outputs are combined to produce the final filtered signal at the high RF data rate, effectively adding a spatial dimension to the processing architecture.
Data Source
AI summary
A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.