Complementary Logic RF Divider Latch for Low-Voltage 10 GHz Operation
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Solution Overview
Problem
Existing high-frequency RF divider circuits face challenges in achieving high operating frequencies while minimizing supply current consumption and maintaining low noise levels, particularly in cellular telephone applications, where they often require large transistors to ensure adequate output signal voltage swings, leading to increased power consumption and limited low supply voltage operation.
Innovation Solution
A complementary logic high-frequency RF divide-by-two circuit utilizing a pair of differential complementary logic latches with a tracking cell and a locking cell, where the locking cell includes a pair of complementary logic inverters and transmission gates, enabling efficient signal communication and reducing supply current consumption by operating at low supply voltages (e.g., 1.3 volts) with high operating frequencies (e.g., 10 GHz).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML latch is used to achieve high operating frequency (10 GHz) and low supply voltage operation, then maximum operating frequency and low supply voltage operation are improved, but power consumption increases to approximately 12 milliamperes
Solution Approach 1:
The patent changes the fundamental logic family from CML to complementary logic, altering the operating parameters including supply voltage requirements and power consumption characteristics. This enables operation at 10 GHz with significantly reduced current consumption compared to CML implementations
Solution Approach 2:
The patent introduces dynamic control through enable transistors that selectively activate or deactivate the tracking cell and locking cell based on the desired operation mode (tracking vs. locking), allowing the circuit to adapt its power consumption and functionality dynamically
2Object-affected harmful factors
If pullup load resistances are made small to reduce noise in CML latch, then noise level is improved, but transistor sizes must be increased to provide adequate current flow, leading to larger implementation size
Solution Approach 1:
The patent changes the load implementation from resistive pull-up loads to active complementary logic transistors, fundamentally altering the output stage characteristics. This eliminates the need for small resistance values and their associated current requirements, reducing both noise and transistor sizing requirements
Solution Approach 2:
The patent replaces the passive resistive load mechanism with an active transistor-based current mirror and complementary logic structure, substituting a simple passive element with an active device that provides both loading and signal regeneration functions
3Use of energy by moving object
If enable transistors are made larger to reduce on-resistance for low supply voltage operation in complementary logic latch, then low supply voltage operation is improved, but operating speed decreases
Solution Approach 1:
The patent uses dynamic enabling and disabling of the tracking cell through clock-controlled enable transistors, allowing the circuit to operate at low supply voltages when tracking is not required while maintaining high speed operation when tracking is enabled
Solution Approach 2:
The patent divides the latch functionality into separate tracking cell and locking cell, each with dedicated enable transistors, allowing independent optimization of each cell's transistor sizes for their specific functions without compromising overall performance
4Adaptability or versatility
If many switching logic elements are used in complementary logic latch, then functionality is improved, but supply current consumption increases at high frequencies
Solution Approach 1:
The patent implements dynamic control where the tracking cell is enabled only during tracking mode and the locking cell is enabled only during locking mode, preventing simultaneous operation of all switching elements and thereby reducing total supply current consumption at high frequencies
Solution Approach 2:
The patent uses periodic clock signals to alternately enable the tracking cell and locking cell, creating a periodic operation pattern that limits the number of simultaneously active switching elements and reduces overall power consumption
Data Source
AI summary
A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.