RF Logic Divider Latch Topology for Low-Current Radios
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Solution Overview
Problem
Conventional RF logic dividers have high current consumption, making them impractical for low current radios.
Innovation Solution
A divider design using cascaded latches with tri-state inverters and resistor-capacitor networks, coupled with a biasing network that includes adjustable current sources, to reduce current consumption and improve dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional dynamic-logic or current mode logic dividers are used in PLL, then the divider can perform frequency division function, but the current consumption becomes very high making it impractical for low current radios
Solution Approach 1:
The divider is segmented into multiple latches (first latch, second latch, third latch) that operate in sequence. Each latch processes a portion of the division operation, allowing the overall function to be achieved with lower current consumption per stage while maintaining operational reliability through the coordinated operation of all stages.
Solution Approach 2:
The divider employs periodic clocking signals (CLK and CLKB) to control the operation of latches in sequence. This periodic action allows each latch to operate only when needed, reducing average current consumption while ensuring the divider maintains its frequency division function through synchronized periodic operation.
2Productivity
If conventional dividers are used to achieve frequency division, then the division function is achieved, but the current consumption increases making it unsuitable for sub-mA radios
Solution Approach 1:
The divider uses dynamic latches that switch between different operational states based on clock signals. The latches dynamically transition between holding and updating states, allowing the circuit to perform frequency division with lower average current consumption compared to static conventional divider designs.
Solution Approach 2:
Different latches in the divider chain have specialized functions optimized for their specific roles in the division process. Each latch is designed with local optimizations that reduce its individual current consumption while contributing to the overall frequency division capability of the system.
Data Source
AI summary
An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.