RF Doubler and Tripler Feedback Balancing Without PLLs
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Solution Overview
Problem
Existing radio frequency doublers and triplers face inefficiencies and complexity in achieving frequency doubling and tripling, often requiring bulky filters and phase-locked loops, which are impractical at high frequencies.
Innovation Solution
A radio frequency doubler and tripler design utilizing a feedback loop to balance differential outputs, eliminating the need for phase-locked loops and bulky filters by controlling DC components to achieve frequency doubling and tripling without phase shifts, using transistors and capacitors to manage alternating and direct current components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase-locked loops and bulky filters are used to achieve frequency doubling and tripling, then frequency multiplication is achieved, but device complexity and power losses increase
Solution Approach 1:
The patent extracts and eliminates the phase-locked loop and bulky filter components from the frequency multiplication circuit, achieving frequency doubling and tripling through a simplified transistor-based architecture that directly processes differential signals without requiring these traditional auxiliary components
Solution Approach 2:
The patent replaces the mechanical/physical filtering approach with an electronic feedback control mechanism using transistors and operational amplifiers, substituting bulky passive filters with active electronic components that achieve the same frequency selection function with reduced size and complexity
2Reliability
If phase-locked loops are used to achieve frequency multiplication, then frequency stability is improved, but locking range becomes narrow
Solution Approach 1:
The patent implements dynamic feedback control through operational amplifiers that continuously monitor and adjust the differential output signals, enabling the circuit to adapt to a wide range of input frequencies and maintain stability without being constrained to a narrow locking range like traditional phase-locked loops
Solution Approach 2:
The patent employs feedback loops that sense the differential output signals and use operational amplifiers to regulate the transistor operating points, ensuring frequency stability through continuous correction while maintaining broad adaptability to different input conditions
3Measurement precision
If bulky filters are used for frequency multiplication, then frequency selectivity is improved, but device volume increases
Solution Approach 1:
The patent changes the operating parameters of the transistors through feedback control, dynamically adjusting their electrical characteristics to achieve sharp frequency selectivity without requiring physically large filter components, thereby maintaining high frequency precision in a compact form factor
Solution Approach 2:
The patent substitutes physical filtering mechanisms with electronic feedback control, replacing bulky mechanical filters with compact electronic circuits that achieve equivalent or superior frequency selectivity through active signal regulation rather than passive frequency rejection
4Productivity
If traditional frequency doubling circuits are used, then frequency multiplication is achieved, but power losses increase
Solution Approach 1:
The patent implements self-balancing through feedback loops where the operational amplifiers automatically adjust the transistor operating points to optimize efficiency, enabling the circuit to maintain high frequency doubling performance with minimal power loss through autonomous regulation rather than requiring external power compensation
Data Source
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AI summary
The present description relates to a radio frequency doubler (1) comprising: a first transistor (T1) and a second transistor (T2) connected in parallel between a first differential output (OUT2+) and a current source (100); a third transistor (T3) connected between the current source (100) and a second differential output (OUT2-); a circuit (106) applying a first DC voltage to the gate of the first transistor (T1) and to the gate of the second transistor (T2), and a second DC voltage (Vbias) to the gate of the third transistor (T3); and a feedback loop (108) controlling the first or second voltage from a difference between the DC components of the differential outputs (OUT2+, OUT2-).