Dummy Pattern Generation for RF IC Calibration Kits
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Solution Overview
Problem
The inconsistency in parasitic RLC characteristics between device-under-test (DUT) and corresponding calibration kits leads to unreliable RF characteristics after de-embedding, affecting the accuracy of SPICE model generation in RF IC design.
Innovation Solution
A method is introduced to generate identical dummy patterns for DUTs and calibration kits by aligning them in unit cells using a common reference point on the chip window layer, ensuring consistent parasitic RLC characteristics through direct copying of DUT dummy patterns to calibration kits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy patterns are generated for DUTs and calibration kits separately based on their individual layouts, then the loading effect in photolithography, etching, and planarization processes is mitigated, but the parasitic RLC characteristics between DUTs and calibration kits become inconsistent
Solution Approach 1:
The chip window layer is divided into multiple unit cells, with each unit cell containing a DUT and its corresponding calibration kit. This segmentation allows for systematic generation and copying of dummy patterns within each unit cell, ensuring consistency across all DUTs and calibration kits while maintaining the ability to mitigate loading effects in manufacturing processes.
Solution Approach 2:
Dummy patterns generated for DUTs in each unit cell are copied to the corresponding calibration kits within the same unit cell. This copying mechanism ensures that both DUTs and calibration kits have identical dummy patterns with the same parasitic RLC characteristics, resolving the inconsistency issue while maintaining manufacturing precision.
2Ease of manufacture
If different dummy patterns are used for DUTs and calibration kits to optimize individual performance, then each component's loading effect is addressed, but the de-embedding process produces false and unreliable RF characteristics
Solution Approach 1:
By ensuring that DUTs and their corresponding calibration kits have identical dummy patterns with matching parasitic RLC characteristics, the invention creates equipotential conditions for the de-embedding process. This allows accurate extraction of intrinsic DUT characteristics by canceling out the consistent parasitic effects, thereby achieving reliable RF characteristic measurements.
3Manufacturing precision
If dummy patterns are added to mitigate loading effects in fabrication processes, then manufacturing quality is improved, but additional parasitic RLC is introduced that complicates de-embedding
Solution Approach 1:
The invention applies homogeneous dummy patterns to both DUTs and calibration kits, ensuring that the additional parasitic RLC introduced by dummy patterns is identical for both. This homogeneity simplifies de-embedding by making the parasitic effects cancelable, thereby reducing the complexity of parasitic RLC management while maintaining manufacturing quality.
Data Source
AI summary
The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.