RF ESD Protection Circuit for Thin-Gate NMOS Voltage Stress
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Solution Overview
Problem
Conventional ESD protection techniques fail to provide adequate protection to thin-gate transistors in RF chips, leading to potential burnout due to high voltages during electrostatic discharge events.
Innovation Solution
An RF ESD protection circuit comprising a first NMOS transistor in a deep n-well, a second and third NMOS transistor with RC networks, and a power clamp circuit, which maintains gate voltages within safe limits during discharge, preventing current flow through the gates of these transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection techniques are used, then ESD protection is provided to the RF chip, but the thin-gate transistor is still susceptible to burnout due to high gate voltage during ESD events
Solution Approach 1:
The patent introduces an intermediary circuit structure consisting of three NMOS transistors (N1, N2, N3) with specific connections. The bulk of N1 is connected to its source and to the source of N3, creating an intermediary connection that prevents high voltage from reaching the gate. This intermediary structure acts as a mediator that decouples the gate from the high-voltage ESD path while still providing ESD protection through the drain-source paths of the transistors.
Solution Approach 2:
The patent changes the electrical parameters of the transistor connections, specifically connecting the bulk to the source rather than to a fixed potential. This parameter change ensures that the gate-to-bulk voltage remains within safe limits during ESD events, as the bulk potential follows the source potential, preventing excessive voltage stress on the thin gate oxide.
2Reliability
If a thin-gate transistor is used in the RF chip, then RF performance is improved, but the transistor's voltage withstand capacity deteriorates
Solution Approach 1:
The patent applies local quality by providing specialized ESD protection only to the thin-gate transistor's gate terminal through the specific bulk connection arrangement. The bulk of N1 is connected to the source, creating a local protection mechanism that maintains the thin gate structure for RF performance while providing enhanced voltage withstand capacity at the critical gate region through the protective circuit topology.
Solution Approach 2:
The circuit structure provides beforehand cushioning by pre-establishing a protective path for the gate. The connection of the bulk to the source and to N3's source creates a voltage-following mechanism that cushions the gate from voltage spikes before they can cause damage. The RC networks on N2 and N3 gates further provide temporal cushioning by controlling the discharge timing.
Data Source
AI summary
An RF ESD protection and system are provided. The RF ESD protection circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first RC network and a second RC network. The first NMOS transistor is formed in a deep N-well. The RF ESD protection circuit of this application can make the voltage at the connection point between the bulk and the source of the first NMOS transistor approach the difference between the gate voltage of the first NMOS transistor and the turn-on voltage of the first NMOS transistor. Thus, the gate-source voltage of the first NMOS transistor is close to its turn-on threshold voltage, without exceeding a maximum possible voltage that the gate of the first NMOS transistor can withstand, ensuring that the first NMOS transistor will not be burned out and is provided with desirable ESD protection.