RF FET Switch Stack Bypass Circuitry for Faster OFF Switching
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Solution Overview
Problem
Existing radio frequency (RF) field effect transistor (FET) switch stacks experience slow switching speeds and voltage snapback issues when transitioning from the ON to the OFF state due to the combination of large gate resistors and transistor device gate capacitance, which do not meet stringent RF circuit design requirements.
Innovation Solution
Incorporating drain-source bypass switches across the drain-source terminals of FET transistors to bypass drain-source resistors during the transition from the ON to the OFF state, reducing the RC time constant and preventing voltage snapback by ensuring the transistors reach a steady OFF state quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger gate resistors are used in FET switch stacks, then linearity and insertion loss are improved, but switching speed deteriorates due to increased RC time constant
Solution Approach 1:
The gate resistor is divided into two segments: a first gate resistor connected in series with the gate terminal, and a second gate resistor connected between the first gate resistor and the gate terminal. This segmentation allows the first gate resistor to provide stability and linearity while the second gate resistor enables faster switching by reducing the effective RC time constant during transitions.
Solution Approach 2:
A bypass switch is introduced as an intermediary component connected in parallel with the second gate resistor. During switching transitions, the bypass switch closes to short out the second gate resistor, effectively removing it from the RC time constant calculation and enabling rapid charging/discharging of the gate capacitance while maintaining the benefits of the first gate resistor.
2Ease of operation
If drain-source resistors are present in the charging paths of gate capacitors, then switching control is simplified, but switching speed deteriorates due to RC time constant
Solution Approach 1:
The drain-source resistor is segmented by introducing a bypass switch that can selectively connect around it. During the charging phase, the bypass switch is open and the drain-source resistor provides controlled charging current. During the discharge phase, the bypass switch closes to create a low-impedance discharge path, effectively bypassing the drain-source resistor and reducing the RC time constant for faster switching.
Solution Approach 2:
The circuit transitions from a static resistor configuration to a dynamic configuration where the bypass switch changes state during operation. This dynamic element allows the circuit to have high resistance during charging (for controlled current) and low resistance during discharging (for fast switching), effectively resolving the speed-control contradiction.
3Speed
If gate bypass switches are implemented to improve transition speed, then switching speed is improved, but snapback issues persist during transitions from ON to OFF state
Solution Approach 1:
The bypass switch is activated in advance during the transition period before the FET fully switches states. By closing the bypass switch early in the transition, the gate capacitance can be rapidly discharged through the low-impedance path created by the bypass switch and drain-source resistor combination, preventing voltage snapback before it occurs and ensuring a clean transition to the OFF state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of drain-source bypass switches significantly improves the switching speed and prevents voltage snapback, meeting the stringent switching requirements of RF circuits.
Implementation Method 1
the RC time constant imposed by a combination of each drain-source resistor with corresponding device gate capacitor
Data Source
AI summary
Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.