RF FET Switch Stack Gate Resistor Bypass for Faster Transitions
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Solution Overview
Problem
Existing RF FET switch stacks experience slow switching times due to the presence of gate resistors, which hinder the efficient transition of FET switches between ON and OFF states.
Innovation Solution
A gate control block with a series combination of nMOS and pMOS transistors is used to bypass the gate resistors during transition states, ensuring both transistors are ON during transition periods and OFF during steady states, with controlled gate voltage transitions to speed up the charging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate resistors are used in RF FET switch stacks, then the switching devices are protected and stable operation is achieved, but the switching time increases and efficiency decreases
Solution Approach 1:
The patent implements a dynamic gate resistor bypass mechanism using control circuitry that automatically switches between bypassing and non-bypassing the gate resistors based on the switching state. During transition states, the bypass path is activated to reduce switching time, while during steady states, the gate resistors remain in the circuit to maintain stability and protection. This dynamic adaptation resolves the contradiction by making the circuit configuration state-dependent rather than fixed.
Solution Approach 2:
The control circuitry detects transition states in advance and activates the bypass path before the actual switching occurs. By preliminarily preparing the low-impedance path during the transition detection phase, the gate nodes can be charged or discharged more quickly when the switching event occurs, thereby reducing the overall switching time while maintaining protection during stable operation.
2Reliability
If gate resistors are present in the circuit, then device protection is ensured, but switching speed and transition efficiency are reduced
Solution Approach 1:
The system dynamically adjusts its configuration by activating a bypass path during transition states to improve switching efficiency, while maintaining the gate resistors in the circuit during steady states to ensure device protection. This dynamic reconfiguration allows the circuit to optimize for speed when needed and for protection when stable, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The invention extracts the gate resistors from the signal path during transition states by activating an alternative bypass path. The control circuitry temporarily removes the gate resistors' impedance effect during switching transitions by routing the control signal through the bypass path, thereby improving switching efficiency while keeping the resistors in place for protection during normal operation.
3Loss of time
If bypass paths are always active, then switching time is reduced, but device protection and stability during steady states are compromised
Solution Approach 1:
The bypass path is implemented as a dynamic element controlled by control circuitry that monitors the switching state. The bypass is activated only during transition states when fast switching is needed, and deactivated during steady states to maintain the protective function of gate resistors. This dynamic control resolves the contradiction by making bypass availability state-dependent rather than continuous.
Solution Approach 2:
The control circuitry acts as an intermediary that manages when the bypass path is active or inactive. It detects transition states and selectively enables the bypass path only when needed for fast switching, while ensuring the gate resistors remain effective during steady states for protection and stability. This intermediary control mechanism协调s between the conflicting requirements of fast switching and steady-state reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces the switching time of RF FET switches by providing a low impedance path during transitions, allowing faster charging of the gate nodes and improving the overall efficiency of the switch stack.
Implementation Method 1
a common gate resistor bypass arrangement comprising at least one series combination of an nMOS transistor and a pMOS transistor connected across the one or more common gate resistors and configured to i) bypass the one or more common gate resistors during at least a transition portion of the one or more transition states
Data Source
AI summary
A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.