RF FET Switch Stack Gate Bypass for Faster Settling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large rail and rung resistors in RF FET switching devices cause significant internal gate settling time during signal transitions, which can be as long as 4 microseconds, hindering efficient switching.
Innovation Solution
A gate resistor bypass arrangement is implemented, where bypass switches are connected across common and ladder resistors during transition states, allowing the input signal to bypass these resistors, thereby reducing the internal gate settling time and enabling faster switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large rail and rung resistors are used in the gate resistor network, then the FET switches can be properly biased and controlled, but the internal gate settling time increases significantly (up to 4 microseconds)
Solution Approach 1:
The patent applies dynamics by making the resistor network configurable - it can switch between high-resistance mode (for proper bias control during steady states) and low-resistance mode (for fast charging during transitions). The bypass switches dynamically reconfigure the circuit topology to optimize performance for the current operational phase.
Solution Approach 2:
The bypass switches are activated before or during the transition phase to pre-establish low-resistance paths for rapid gate charging. This preliminary action of switching bypass elements in place ensures that when the transition occurs, the gates can be charged quickly without being limited by the large resistor values used for bias control.
2Reliability
If large rail and rung resistors are used to bias the FET stack, then the switching devices can be properly controlled, but the switching speed decreases due to extended settling time
Solution Approach 1:
The resistor network transitions from a static configuration to a dynamic one where bypass switches can short out the large rail and rung resistors during switching transitions. This dynamic reconfiguration allows the system to have both large resistors (for control) and effectively small resistors (for speed) at different times.
Solution Approach 2:
The patent extracts the problematic large resistors from the signal path during transitions by using bypass switches to create alternative low-resistance paths. The large resistors are effectively removed from the charging path when fast switching is needed, while remaining in place for bias control during steady states.
3Loss of time
If bypass switches are connected across the gate resistors during transition states, then the switching time is reduced, but the device complexity increases
Solution Approach 1:
The bypass switches serve multiple functions: they provide fast charging paths during transitions, maintain proper bias control during steady states when open, and can be controlled by the same control signals that drive the FET switches. This multi-functionality justifies the added complexity by delivering multiple benefits from the same components.
Data Source
AI summary
A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.