RF FET Switch Stack Gate Resistor Bypass for Faster Switching
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Solution Overview
Problem
Existing RF FET switch stacks face challenges in reducing switching time due to the presence of gate resistors, which hinder fast transitions between ON and OFF states.
Innovation Solution
A dynamic gate control block is introduced, comprising a series combination of nMOS and pMOS transistors that bypass the common gate resistors during transition states, allowing for low impedance status and efficient signal feeding, while maintaining high impedance during steady states to prevent bypassing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate resistors are used in RF FET switch stacks, then the circuit stability and control are improved, but the switching time increases and switching speed deteriorates
Solution Approach 1:
The patent applies dynamic resistance switching by using a bypass transistor (MN) that can dynamically change the effective gate resistance. During switching transitions, the bypass transistor turns ON to provide a low-impedance path that shorts the gate resistor, enabling fast charging/discharging of gate capacitance. During steady states, the bypass transistor turns OFF to restore the original gate resistor functionality for stable bias control. This dynamic reconfiguration resolves the contradiction by having low resistance only when needed for fast switching.
Solution Approach 2:
The patent extracts the gate resistor from the signal path during switching transitions by activating the bypass transistor. The bypass transistor effectively removes the gate resistor's influence on the switching transient by providing an alternative low-impedance path for gate current, allowing the gate capacitance to charge/discharge rapidly without being limited by the gate resistor value.
2Manufacturing precision
If gate resistors are used in RF FET switch stacks, then the bias control precision is improved, but the switching speed deteriorates
Solution Approach 1:
The bypass transistor dynamically adjusts the gate resistance based on the switching state. During transitions, it creates a low-impedance path for rapid voltage changes at the gate, achieving fast switching speeds. During steady states, it disconnects to allow the gate resistor to provide precise bias control. This time-dependent behavior resolves the speed-precision contradiction.
3Device complexity
If common gate resistors are used for multiple FET switches, then the device complexity is reduced, but the switching time for each individual switch increases
Solution Approach 1:
The patent introduces a bypass transistor for each FET switch that can be independently controlled. During switching transitions, each bypass transistor activates to short its associated common gate resistor, enabling fast individual switching despite the shared resistor structure. During steady states, all bypass transistors deactivate to maintain the simplified common gate resistor configuration. This resolves the contradiction by dynamically enabling fast individual switching while preserving the simplicity of the common gate resistor architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces switching time by enabling efficient resistor bypassing during transitions, thereby improving the switching speed and reliability of RF FET switch stacks.
Implementation Method 1
a common gate resistor bypass arrangement comprising at least one series combination of an nMOS transistor and a pMOS transistor connected across the one or more common gate resistors and configured to i) bypass the one or more common gate resistors during at least a transition portion of the transition state
Implementation Method 2
the nMOS transistor and the pMOS transistor being both in an ON state during said transition portion
Data Source
AI summary
A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.