RF FET Switch Stack Gate Feeds for Faster Switching
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Solution Overview
Problem
Existing RF switch stacks experience prolonged switching times due to the direct proportionality of RC time constants with the number of FETs, particularly in long stacks, leading to delayed gate and body node transitions.
Innovation Solution
Implementing multiple gate and body feed arrangements with bypass switches across common resistors, allowing for separate control signals to be fed at different heights of the stack, reducing the RC time constant and enhancing settling times by distributing the charging process vertically and horizontally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single gate feed arrangement is used in RF FET switching devices, then the device structure is simple, but the switching time is prolonged due to increased RC time constants
Solution Approach 1:
The patent divides the single gate feed arrangement into multiple segmented feed arrangements (first gate feed arrangement and second gate feed arrangement) positioned at different locations. This segmentation reduces the RC time constant by distributing the charging path, thereby decreasing switching time while managing device complexity through structured multiplication of components.
Solution Approach 2:
The patent introduces a spatial dimension to the gate feed arrangement by positioning feeds at different locations (first and second gate feed arrangements at different heights/positions). This dimensional approach creates multiple charging paths through space, reducing the effective RC time constant and improving switching speed without merely increasing component count in a single plane.
2Strength
If the number of FETs in the stack is increased, then the voltage handling capability is improved, but the RC time constant increases proportionally, delaying gate and body node transitions
Solution Approach 1:
The patent segments the gate feed arrangement into multiple distributed feeds along the FET stack. This segmentation creates parallel charging paths that reduce the effective RC time constant, allowing the stack to maintain high voltage handling capability while reducing the time penalty associated with transitioning gate and body nodes in long stacks.
Solution Approach 2:
The patent applies local quality by positioning gate feed arrangements at specific locations (different heights) along the FET stack. This localized feeding approach optimizes the charging characteristics for different segments of the stack, reducing overall transition time while preserving the voltage handling capability of the complete stack structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the RC time constant, improving the settling profile by approximately half, thereby accelerating the switching process and enabling faster transitions in RF switch stacks.
Implementation Method 1
each gate feed arrangement being coupled to the stacked arrangement at a different height of the stacked arrangement and comprising one or more bypass switches connected across one or more common gate resistors
Implementation Method 2
improving the settling profile by approximately half, thereby accelerating the switching process
Data Source
AI summary
An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.