RF FET Switch Stack Gate Feeds for Faster Settling

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Solution Overview

Problem

Existing RF switch stacks experience prolonged switching times due to the direct proportionality of RC time constants with the number of FETs, particularly in long stacks, leading to delayed settling times for gate and body nodes farthest from the center feed.

Innovation Solution

Implementing multiple gate and body feed arrangements at varying heights within the stack, including bypass switches across common resistors, to reduce the RC time constant and enhance settling times, with embodiments showing improvements by reducing the number of bypass switches and optimizing feed locations to balance layout constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single center feed arrangement is used in RF FET switch stacks, then the layout is simplified and device complexity is reduced, but the RC time constant increases and settling time is prolonged

Engineering Contradiction:

Improvefeed network structureVSAvoidsettling time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent divides the single center feed arrangement into multiple feed arrangements positioned at different heights within the FET switch stack. This segmentation reduces the RC time constant by providing multiple charging paths, thereby decreasing the settling time while maintaining manageable device complexity through systematic distribution of feed points.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the feed network by positioning feed arrangements at different heights within the stack rather than using a single horizontal feed point. This spatial distribution across multiple levels reduces the effective RC time constant and accelerates settling time without significantly increasing overall device complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If multiple gate feed arrangements are implemented at varying heights, then the RC time constant is reduced and settling time is improved, but the device complexity and layout constraints increase

Engineering Contradiction:

Improvesettling timeVSAvoidfeed network structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies local quality by positioning feed arrangements at specific heights corresponding to different sections of the FET switch stack. Each local feed point optimizes the charging characteristics for its corresponding region, reducing overall settling time while managing complexity through localized rather than uniform distribution.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the spatial parameter of feed arrangement positions from a single center point to multiple distributed points at varying heights. This parameter modification reduces the RC time constant and settling time while the systematic arrangement manages the increase in device complexity.

Inventive Principle:

Principle #35Parameter changes

3Speed

If bypass switches are added across common resistors in feed arrangements, then the switching speed is enhanced and settling time is reduced, but the number of components and device complexity increase

Engineering Contradiction:

Improveswitching speedVSAvoidnumber of components

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The bypass switches are configured to preemptively provide alternative current paths during switching transitions. By having these bypass paths pre-positioned across common resistors in the feed arrangements, the system can rapidly redirect current during state changes, enhancing switching speed while the structured implementation manages component complexity.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of multiple feed arrangements significantly reduces the RC time constant, speeding up internal charging and improving settling times, with embodiments achieving settling times approximately half that of single-center-fed configurations, while maintaining layout feasibility.

Implementation Method 1

The implementation of multiple feed arrangements significantly reduces the RC time constant, speeding up internal charging and improving settling times

Methodology Applied

Scientific EffectRC time constant reduction: Capacitance

Implementation Method 2

each gate feed arrangement being coupled to the stacked arrangement at a different height of the stacked arrangement and comprising one or more bypass switches connected across one or more common gate resistors

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11671135B2Methods and apparatus for reducing switching time of RF FET switching devices

Publication Date: 2023.06.06 PSEMI CORP

AI summary

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.