RF FET Switch Stack Gate Bypass for High-Impedance Steady States

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Solution Overview

Problem

Existing RF switch FET stacks with gate resistor networks face challenges in reducing switching time due to the high impedance status during steady states and transition states, which affects the efficiency of RF signal switching.

Innovation Solution

A dynamic gate control block is introduced, comprising a series combination of nMOS and pMOS transistors that bypass the common gate resistors during transition states while maintaining high impedance during steady states, allowing for efficient RF signal switching by controlling the gate voltages of the transistors to establish low impedance status during transitions and high impedance status during steady states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate resistors are used in the FET switch stack, then the high impedance status is maintained during steady states, but the switching time increases due to the impedance limiting the charging/discharging speed of gate capacitance

Engineering Contradiction:
Improvehigh impedance status during steady stateVSAvoidswitching time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies the dynamics principle by making the gate resistor impedance dynamic rather than static. A bypass switch (controlled by control signals) is connected in parallel with the gate resistors, allowing the impedance to switch between high (during steady state) and low (during transition). This dynamic impedance change enables the circuit to maintain high impedance for stability during steady states while providing low impedance paths during transitions to rapidly charge/discharge gate capacitance, thereby reducing switching time without compromising steady-state performance.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If gate resistors are used to control FET gates, then the FET switches can be properly biased, but the resistors create stress on the transistors during switching transitions

Engineering Contradiction:
ImproveFET gate bias controlVSAvoidstress on transistors during switching
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies the intermediary principle by introducing a bypass switch as a mediator between the control signal and the FET gate. During transition periods, the bypass switch activates and provides an alternative low-impedance path that shields the FET from the full stress of rapid voltage changes through the gate resistor. The bypass switch acts as an intermediary that handles the high-current switching transient, while the gate resistor continues to provide gentle bias control, thereby reducing stress on the FET transistor during switching transitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces switching time and improves the efficiency of RF signal switching by effectively bypassing the gate resistors during transitions, thereby reducing stress on the transistors and enhancing the reliability of the RF switch FET stacks.

Implementation Method 1

bypass the one or more common gate resistors during at least a transition portion of the transition state... establishing a low impedance status during transitions

Methodology Applied
Scientific EffectElectrical Impedance: Electrical Resistance

Implementation Method 2

the nMOS transistor and the pMOS transistor being both in an ON state during said transition portion... one of the nMOS transistor and the pMOS transistor being in an OFF state

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS11405035B1Gate resistor bypass for RF FET switch stack
Publication Date: 2022.08.02 PSEMI CORP
  • US11405035B1 patent drawing
  • US11405035B1 patent drawing
  • US11405035B1 patent drawing

AI summary

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.