RF FET Stack Layout for Higher Voltage Handling and Lower Ron
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Solution Overview
Problem
Radio-frequency (RF) switches face challenges in achieving high voltage handling capability and low ON-resistance (Ron) while maintaining linearity performance, especially when subjected to high peak RF voltages and power applications, where parasitic effects and degradation in Ron performance occur.
Innovation Solution
The implementation of a stack configuration with field-effect transistors (FETs) having a non-uniform distribution of parameters such as gate length, which allows for improved voltage handling capacity and reduced ON-resistance by varying the gate lengths and widths of FETs, optimizing the distribution of voltage across the stack to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If FETs are arranged in a stack configuration to increase voltage handling capability, then voltage handling capability is improved, but ON-resistance increases
Solution Approach 1:
The patent applies local quality by assigning different gate lengths to different FETs within the stack based on their position. Specifically, FETs experiencing higher voltage stress (typically those closer to the input terminal) are given longer gate lengths to enhance their voltage handling capability, while FETs experiencing lower voltage stress are given shorter gate lengths to minimize their contribution to overall ON-resistance. This non-uniform distribution of gate lengths optimizes the trade-off between voltage handling and ON-resistance at local levels throughout the stack.
Solution Approach 2:
The patent implements parameter changes by varying the gate length parameter across different FETs in the stack. The gate length is adjusted as a continuous or discrete parameter depending on the voltage stress each FET experiences. This parameter variation allows each FET to be optimized for its specific operating conditions, thereby improving the overall performance of the stack in terms of both voltage handling capability and ON-resistance.
2Strength
If gate length is increased to improve voltage handling, then voltage handling capability is improved, but linearity performance degrades
Solution Approach 1:
The patent applies local quality by strategically placing longer gate lengths only in FETs that require enhanced voltage handling capability due to higher voltage stress, while maintaining shorter gate lengths in FETs where linearity is more critical. This localized optimization ensures that linearity performance is preserved in regions where it matters most, while voltage handling is enhanced where needed.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the gate length parameter based on the voltage stress conditions of each FET. By changing the gate length parameter in a non-uniform manner across the stack, the patent achieves a balance between voltage handling capability and linearity performance, avoiding the uniform degradation that would occur if all gate lengths were increased.
3Power
If stack height is increased to handle higher power, then power handling capability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing a systematic approach to gate length distribution that simplifies the design process. Instead of requiring complex individual optimization of each FET, the patent provides a rule-based method for determining gate lengths based on position and voltage stress, thereby managing device complexity while achieving high power handling capability.
Solution Approach 2:
The patent implements parameter changes through a scalable approach where the gate length parameter is adjusted based on the number of FETs in the stack and their positions. This parameter-based design allows the stack to be easily scaled to different power levels by simply changing the number of FETs and applying the same gate length distribution rules, thereby avoiding exponential increases in device complexity.
Data Source
AI summary
Methods related to radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a method for fabricating an RF switching device can include: providing a semiconductor substrate; forming a plurality of field-effect transistors (FETs) on the semiconductor substrate such that the FETs have a non-uniform distribution of a parameter; and connecting the FETs to form a stack, such that the non-uniform distribution results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.