RF Filter Packaging Layout for Lower Parasitic Inductance
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Solution Overview
Problem
Existing RF filters face challenges in achieving high out-of-band suppression and isolation due to parasitic inductance introduced by redistribution lines and through holes, which affects edge roll-off and overall performance, especially in devices like diplexers and multiplexers.
Innovation Solution
A novel RF filter structure is designed with a specific layout of micro bumps, redistribution lines, and micro through holes to reduce parasitic inductance, enhancing edge roll-off and out-of-band suppression by optimizing the electrical connections between substrates and parallel resonant arms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution lines and through holes are used to connect substrates, then electrical connection is achieved, but parasitic inductance increases affecting edge roll-off and out-of-band suppression
Solution Approach 1:
The patent divides the electrical connection path into multiple segments by using multiple micro through holes and intersecting redistribution lines. This segmentation reduces the inductance of each individual connection path, as the current has multiple parallel routes rather than a single long path, thereby reducing total parasitic inductance while maintaining electrical connection functionality.
Solution Approach 2:
The patent utilizes three-dimensional spatial arrangement by having redistribution lines from different layers intersect and connect through micro through holes. This dimensional approach allows creating multiple parallel current paths in the vertical and horizontal dimensions simultaneously, reducing parasitic inductance through parallel path effects without increasing the planar footprint.
2Ease of operation
If micro bumps, redistribution lines, and through holes are added for electrical connection, then substrate connectivity is improved, but additional inductance is introduced reducing filter performance
Solution Approach 1:
The patent merges multiple redistribution lines and micro through holes into an integrated connection structure where multiple paths converge and intersect. This merging creates parallel current paths that reduce overall inductance while providing robust electrical connectivity between substrates, thereby improving connectivity without sacrificing filter performance.
Solution Approach 2:
The patent creates multiple copies of connection paths by using multiple micro through holes and intersecting redistribution lines. Instead of relying on a single connection path, multiple redundant paths are created, which reduces the inductance of each path through parallel effect and provides backup connectivity, thus improving both connectivity and maintaining filter performance.
Data Source
AI summary
A semiconductor device including a first functional module arranged on a first substrate and having a chip, an electrical connection component and a sealing ring, where the sealing ring surrounds the chip, and the chip is electrically connected to the electrical connection component; a second functional module having a packaging substrate, where the packaging substrate includes at least two metal layers and a dielectric layer between the metal layers; a third functional module having multiple redistribution lines and multiple micro through holes for electrical connection between the first functional module and the second functional module, where the electrical connection component in the first functional module is electrically connected to the third functional module; and a second substrate, where the second substrate is sealed with the first substrate.