RF Filtering Circuit Using Shift Registers for 60-GHz Sidelobe Suppression
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Solution Overview
Problem
Existing radio frequency signal filtering circuits face challenges in efficiently concentrating power within a specific frequency range, particularly in the 60-GHz band, leading to insufficient filtering of secondary lobes and excessive power transmission outside the desired range.
Innovation Solution
A radio frequency transmitter incorporating a filtering circuit with a series/parallel shift register and an adder circuit, utilizing coefficients calculated based on the pulse response of an interpolation filter to achieve efficient filtering, where the shift register implements frequency shifts and the adder circuit combines analog signals to produce a filtered output, effectively concentrating power within the desired frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional filtering circuits are used to shape radio frequency signals in the 60-GHz band, then signal transmission is enabled, but the circuit surface area and complexity become excessive
Solution Approach 1:
The filtering function is segmented into discrete tapped delay line elements, each contributing a specific delayed version of the input signal. This segmentation allows the complex filtering operation to be broken down into simpler, modular components that can be implemented with standard circuit elements, reducing overall circuit complexity while maintaining the required filtering performance for 60-GHz band signals
Solution Approach 2:
The invention changes the implementation parameters by using a tapped delay line structure with specific tap weights instead of conventional filter topologies. By adjusting the delay times and amplitude weights of each tap, the filter response can be optimized for the 60-GHz band without requiring large circuit areas, thus reducing device complexity while maintaining transmission compliance
2Reliability
If conventional filtering circuits are used to shape radio frequency signals in the 60-GHz band, then signal transmission is enabled, but the circuit surface area becomes excessive
Solution Approach 1:
The tapped delay line structure implements a nested arrangement where delayed versions of the signal are combined in a hierarchical manner. Each tap contributes a delayed and weighted version of the input, with the combinations nested within the overall filter structure. This nesting allows efficient use of circuit area by reusing signal paths and combining multiple filtering functions within a compact architecture suitable for 60-GHz band applications
Solution Approach 2:
The invention transitions from traditional time-domain filter designs to a structure that exploits the frequency-domain characteristics of the 60-GHz band. By designing the tapped delay line with specific delay intervals and tap weights that correspond to the spectral requirements of 60-GHz communication, the filter achieves the required performance in a more area-efficient manner by operating in a different dimensional space (frequency domain optimization)
3Reliability
If conventional filtering methods are used, then signal transmission is possible, but secondary lobes are not sufficiently filtered resulting in excessive power transmission outside the desired range
Solution Approach 1:
The tapped delay line filter provides implicit feedback by combining multiple delayed versions of the input signal with specific weights. This feedback mechanism allows the filter to cancel out unwanted spectral components including secondary lobes through destructive interference, while reinforcing the desired frequency components through constructive interference. The result is effective suppression of power transmission outside the desired frequency range while maintaining signal transmission capability within the band
Data Source
AI summary
In embodiments, a radio frequency transmitter comprising at least one filtering circuit is provided. The filtering circuit includes a series/parallel shift register comprising a binary input and N binary outputs, with N being an integer greater than or equal to OSR, OSR being an integer greater than or equal to 2. The binary outputs ranging from 0 to N−1, the register receiving a binary data signal at a data frequency on its input and implementing shifts on the N binary outputs at a frequency equal to a multiplier of the data frequency and OSR. The filtering circuit further comprising a first circuit defined by N coefficients Ci. For each non-zero coefficient Ci, a signal determined by the coefficient Ci and by the corresponding one of the binary outputs. The filtering circuit further comprising and an adder circuit delivering an output equal to the sum of analog signals.