RF Flash ADC AC-Coupled References for Low-Parasitic Linearity

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Solution Overview

Problem

Flash ADCs face limitations in high-SNR and high-SFDR applications due to nonlinearities and parasitic capacitance issues in comparator designs, which degrade SNR and SFDR, making it challenging to achieve high performance in multi-GHz applications.

Innovation Solution

The use of AC-coupled references and interpolation techniques in Flash ADCs, which simplify comparator structures, reduce parasitic capacitances, and enable power-up offset calibration, allowing for improved linearity and reduced complexity in comparator designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional comparator designs are used in Flash ADCs, then the basic conversion function is achieved, but nonlinearities and parasitic capacitance degrade SNR and SFDR performance

Engineering Contradiction:
ImproveSNR and SFDRVSAvoidnonlinearities and parasitic capacitance
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the problematic parasitic capacitances and nonlinearities from the comparator design by using AC-coupled references that isolate the reference voltage from parasitic capacitance sources, thereby eliminating the harmful factors that degrade SNR and SFDR while preserving the basic comparison function

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operating parameters of the comparator by implementing power-up offset calibration that adjusts the reference voltage levels to compensate for nonlinearities, thereby improving measurement precision (SNR and SFDR) without requiring fundamental redesign of the comparator architecture

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If complex comparator structures are used to improve linearity, then SNR and SFDR improve, but device complexity and parasitic capacitance increase

Engineering Contradiction:
ImprovelinearityVSAvoidcomparator structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing offset calibration during power-up before the ADC operates in normal mode. This preliminary calibration step pre-adjusts the reference voltages to compensate for nonlinearities, achieving improved linearity without requiring complex continuous correction circuitry during operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary calibration mechanism that mediates between the simple comparator structure and the requirement for high linearity. The AC-coupled references act as an intermediary element that enables precise voltage comparison while isolating the simple comparator from parasitic capacitance and nonlinearities

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If AC-coupled references and interpolation techniques are used, then parasitic capacitance is reduced and linearity is improved, but circuit complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidcomparator structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the reference voltage generation into separate AC-coupled reference paths for each comparator. This segmentation isolates each comparator's reference from parasitic capacitance sources while maintaining simplicity through modular, repetitive structure rather than complex interconnections

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10587281B2Radio frequency flash ADC circuits
Publication Date: 2020.03.10 MAXLINEAR ASIA SINGAPORE PTE LTD
  • US10587281B2 patent drawing
  • US10587281B2 patent drawing
  • US10587281B2 patent drawing

AI summary

A system and method for sampling an RF signal uses a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.