RF Receiver Frame Timing to Whiten Digital Processing Interference

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current RF receiver integrated circuits face performance degradation due to frequency domain interference caused by periodic current pulses from digital frame processing, which interfere with the RF signals being received and processed.

Innovation Solution

The implementation of a variable time delay in the frame control signals that initiate digital frame processing, achieved by waiting a variable number of digital clock cycles or performing no-operation cycles, to whiten the frequency domain interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If digital frame processing is performed using periodic digital clocks, then digital processing operations can be executed efficiently, but frequency domain interference is generated that degrades RF signal reception performance

Engineering Contradiction:
Improvedigital processing efficiencyVSAvoidfrequency domain interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the frame processing interval variable rather than fixed. The controller dynamically adjusts the time interval between consecutive frame processing operations based on detected interference levels, transforming a static periodic system into a dynamic adaptive one that can respond to and mitigate interference conditions while maintaining processing efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the temporal parameter of frame processing by introducing variable time intervals between processing operations. Instead of using a fixed periodic clock signal, the system modifies the timing parameter dynamically, which spreads the spectral energy of processing operations across a wider frequency range, thereby reducing concentrated frequency domain interference

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If fixed time intervals are used for frame processing, then processing operations are synchronized and efficient, but concentrated frequency domain interference occurs at specific frequencies

Engineering Contradiction:
Improveprocessing synchronizationVSAvoidconcentrated frequency interference
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The system transitions from static fixed intervals to dynamic variable intervals, where the time between frame processing operations is continuously adjusted based on interference detection, allowing the system to maintain operational efficiency while eliminating concentrated spectral interference

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent modifies periodic action by making the period variable. Instead of uniform periodic processing, the system uses non-uniform periodic intervals that adapt based on detected interference conditions, effectively spreading spectral energy while maintaining the rhythmic nature of processing operations

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9312899B2Radio frequency (RF) receivers having whitened digital frame processing and related methods
Publication Date: 2016.04.12 SKYWORKS SOLUTIONS INC
  • US9312899B2 patent drawing
  • US9312899B2 patent drawing
  • US9312899B2 patent drawing

AI summary

Radio frequency (RF) receivers having whitened digital frame processing and related methods are disclosed. Disclosed embodiments whiten frequency domain interference generated periodic current pulses from by digital frame processing by applying a variable time delay to the frame control signals that initiate digital frame processing. For one embodiment, the variable time delay is achieved by waiting a variable number of digital clock cycles for each digital frame processing cycle. Still further, a variable number of no operation (NO-OP) cycles can be performed at the beginning of each frame processing cycle to provide the variable time delay for the variable number of digital clock cycles. Other variable time delay techniques could also be utilized while still taking advantage of the whitened digital frame processing embodiments described herein.