RF Transistor Stack Gate Capacitor Coupling for Parasitic Limits
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Solution Overview
Problem
Existing stacked transistor amplifiers face challenges in achieving practical realization of large stack heights due to decreasing capacitance values of gate capacitors approaching parasitic/stray capacitance levels, making it difficult to maintain desired voltage distribution across transistors, especially as the number of transistors increases.
Innovation Solution
The proposed solution involves a monolithically integrated circuital arrangement where gate capacitors of adjacent or non-adjacent transistors are coupled to increase capacitance values, allowing for a desired distribution of RF voltage across the transistors while maintaining efficient operation, by connecting gate capacitors in a way that enhances capacitance values beyond parasitic/stray capacitance levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of transistors in the stack increases to achieve higher output power, then the output power increases, but the capacitance values of gate capacitors decrease to values approaching parasitic/stray capacitance, making practical realization challenging
Solution Approach 1:
The patent combines multiple gate capacitors in parallel to achieve the required capacitance values. Specifically, gate capacitors are connected in parallel between the gate and source of cascode transistors, allowing the capacitances to add up and reach the necessary values without requiring individually large capacitors that would be difficult to implement at higher stack heights.
Solution Approach 2:
The patent introduces an additional capacitive element by connecting a capacitor between the gate of the output transistor and the drain of the input transistor. This adds a new dimension to the capacitor network, providing an additional path for capacitance contribution and enabling practical implementation of high-stack configurations.
2Stability of the object's composition
If gate capacitor capacitance values are reduced to maintain voltage distribution in higher stacks, then voltage distribution is maintained, but the capacitance values approach parasitic/stray capacitance levels, rendering practical realization challenging
Solution Approach 1:
The patent merges multiple capacitance contributions from different gate capacitors and the additional capacitor to achieve the required total capacitance values. This combination approach allows maintaining adequate capacitance values even in high-stack configurations where individual capacitor values would otherwise need to be extremely small.
Solution Approach 2:
The additional capacitor connected between the gate of the output transistor and the drain of the input transistor acts as an intermediary element. It provides an additional capacitive path that mediates the voltage distribution across the stack, helping to maintain stable voltage distribution without requiring individually small gate capacitor values.
3Power
If stack height is increased to achieve higher output power, then output power increases, but the gate capacitor capacitance values become too small to distinguish from parasitic/stray capacitance
Solution Approach 1:
The patent combines capacitance from multiple gate capacitors and the additional capacitor to achieve sufficient total capacitance values. This merging of capacitance sources allows maintaining manufacturing precision by using larger, more controllable capacitor values rather than relying on very small individual capacitor values that would be difficult to control.
Solution Approach 2:
By adding the capacitor between the gate of the output transistor and the drain of the input transistor, the patent introduces an additional dimension to the capacitor network. This provides an extra degree of freedom in capacitance design, allowing for better control of total capacitance values and improving manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the practical implementation of higher stack heights with larger output power or the use of smaller size transistor devices, while maintaining the desired voltage distribution and efficiency, thus overcoming the limitations of previous configurations.
Implementation Method 1
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors
Data Source
AI summary
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.