RF-Driven Gate Driver for NFC Display Scanning
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Solution Overview
Problem
Existing display systems face challenges in efficiently controlling pixel arrays using gate driver circuits, particularly when sensing near-field communication signals, as they require precise clock and voltage signals to initiate scanning operations effectively.
Innovation Solution
A display system comprising a pixel array, an antenna, and a reader circuit that generates and transmits radio frequency signals to a gate driver circuit, enabling the generation of control voltages and clock signals to control the pixel array, allowing for efficient scanning operations upon sensing near-field communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driver circuit uses traditional clock and voltage signals from a circuit board, then the display system has stable operation, but the system complexity increases and responsiveness to near-field communication decreases
Solution Approach 1:
The patent extracts the clock signal generation function from the external circuit board and relocates it to the reader circuit on the display panel. The reader circuit generates the clock signal locally based on received RF signals, eliminating the need for complex external clock distribution while maintaining stable operation.
Solution Approach 2:
The reader circuit acts as an intermediary that converts RF signals from near-field communication into usable clock signals and control voltages for the gate driver circuit. This intermediary function enables direct control without requiring a traditional circuit board interface.
2Adaptability or versatility
If the gate driver circuit waits for initial signal from reader circuit, then near-field communication sensing is enabled, but the scanning operation is delayed
Solution Approach 1:
The reader circuit continuously monitors for near-field communication signals and prepares the clock signal generation in advance. When an RF signal is detected, the clock signal generation is immediately initiated without waiting for external commands, reducing scanning delay while maintaining NFC sensing capability.
3Speed
If the display system integrates reader circuit and gate driver circuit on the same panel, then the system responds faster to near-field communication, but the circuit design becomes more complex
Solution Approach 1:
The patent merges the reader circuit and gate driver circuit functions onto the same display panel, integrating RF signal reception, clock signal generation, and pixel array control in a unified structure. This integration eliminates signal transmission delays between separate components while managing circuit complexity through shared infrastructure.
Solution Approach 2:
The reader circuit is designed with multi-functionality, serving both as an RF signal receiver and as a clock signal generator for the gate driver circuit. This universal design reduces the need for separate dedicated components, simplifying the overall circuit architecture while improving responsiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively initiates and controls pixel array scanning by generating necessary control voltages and clock signals from received radio frequency signals, enhancing the display system's responsiveness and functionality during near-field communication events.
Implementation Method 1
The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication
Implementation Method 2
The reader circuit is configured to receive the RF signal and generate a clock signal according to the RF signal
Data Source
AI summary
A display system includes a pixel array, an antenna, a reader circuit, and a gate driver circuit. The antenna is configured to transmit a radio frequency (RF) signal in response to a wireless communication. The reader circuit is coupled to the antenna and is configured to receive the RF signal. The gate driver circuit is coupled to the reader circuit and the pixel array. The reader circuit is further configured to generate a clock signal according to the RF signal and transmit the clock signal to the gate drive circuit. The gate driver circuit is configured to generate scanning signals according to the clock signal and transmit the scanning signals to the pixel array.