RF Gate Oxide Layout for Lower STI Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current RF devices suffer from higher resistance and large parasitic capacitance, affecting their overall performance.
Innovation Solution
A method involving a substrate with a core and non-core region, shallow trench isolation, and a specific gate oxide layer formation process to minimize exposure of the STI surface during patterning, reducing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate oxide layer formation process is used, then the fabrication process is simple, but the STI surface is excessively exposed leading to increased parasitic capacitance and resistance
Solution Approach 1:
The gate oxide layer formation process is segmented into multiple stages: first forming a thick gate oxide layer, then selectively removing portions in different regions, and finally forming a thin gate oxide layer in the core region. This segmentation allows precise control of STI exposure in different areas, reducing parasitic capacitance and resistance while maintaining process feasibility.
Solution Approach 2:
Different gate oxide layer configurations are applied to different regions: the non-core region retains a thick first gate oxide layer that minimally exposes the STI surface, while the core region receives a thin second gate oxide layer. This local differentiation optimizes RF device performance by reducing parasitic effects in the non-core region while maintaining proper electrical characteristics in the core region.
2Reliability
If the STI surface is fully exposed during patterning, then the patterning process is straightforward, but parasitic capacitance and resistance increase significantly
Solution Approach 1:
A thick first gate oxide layer is formed preliminarily across the entire substrate before patterning. This preliminary layer serves as a protective barrier during subsequent processing steps, preventing excessive STI surface exposure and reducing parasitic capacitance and resistance while still allowing the patterning process to proceed.
Solution Approach 2:
The first gate oxide layer acts as an intermediary protective layer between the STI surface and the external environment during patterning. It mediates the conflict between straightforward patterning and parasitic reduction by providing a controllable barrier that can be selectively removed to expose only necessary portions of the STI surface.
3Reliability
If a thick gate oxide layer is formed to reduce STI exposure, then parasitic capacitance is reduced, but the device area increases
Solution Approach 1:
A thick first gate oxide layer is formed only in the non-core region where it is needed for parasitic reduction, while the core region receives a thin second gate oxide layer. This local application of different thicknesses reduces parasitic capacitance without unnecessarily increasing the overall device area, as the thick layer is confined to regions where it provides the most benefit.
Solution Approach 2:
Instead of forming a uniformly thick gate oxide layer across the entire device (which would increase area), the thick first gate oxide layer is applied partially only in the non-core region. This partial action achieves sufficient parasitic reduction without the area penalty of a completely thick gate oxide structure.
Data Source
AI summary
A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.