RF IC Self-Testing via Parallelized Processing Units
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated RF circuits in semiconductor devices makes traditional RF testing time-consuming and costly, as it requires expensive automatic test equipment (ATE) to generate and process RF signals for identifying 'good' and 'bad' ICs during production.
Innovation Solution
An integrated circuit (IC) with an RF transmitter and receiver, along with parallelized processing units such as CPU, GPU, or DSP, that can generate and process RF signals internally to perform self-testing, reducing the need for external ATE and simplifying the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ATE is used to generate and process RF signals for testing, then measurement precision and reliability are improved, but device complexity and cost increase
Solution Approach 1:
The IC performs self-testing by generating RF test signals internally through its own RF transmitter and processing the received signals through its RF receiver and computation unit, eliminating the need for external ATE to generate and process RF signals
Solution Approach 2:
The patent extracts the RF signal generation and processing functions from the external ATE and relocates them into the IC itself, allowing the device to test itself without requiring complex external equipment
2Measurement precision
If traditional ATE is used for RF testing, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The IC performs self-testing by generating RF test signals internally through its own RF transmitter and processing the received signals through its RF receiver and parallelized computation units, eliminating the need for external ATE and reducing testing time
Solution Approach 2:
The computation unit dynamically allocates multiple processing units to parallelize the test procedures, adapting the processing capacity to the complexity of the RF functions being tested to reduce overall testing time
3Adaptability or versatility
If more RF functions are integrated into a single chip, then adaptability is improved, but loss of time increases
Solution Approach 1:
The computation unit dynamically allocates multiple processing units to parallelize the test procedures for multiple RF functions, adapting the processing capacity to the complexity and number of RF functions being tested simultaneously
Solution Approach 2:
The patent segments the testing of multiple RF functions into parallel test procedures, with each processing unit handling specific RF function tests simultaneously, thereby reducing the total testing time while maintaining comprehensive coverage of all integrated RF functions
4Measurement precision
If traditional ATE is used for testing, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The IC performs self-testing by generating RF test signals internally through its own RF transmitter and processing the received signals through its RF receiver and computation unit, eliminating the need for expensive external ATE equipment
Solution Approach 2:
The patent extracts the RF signal generation and processing functions from the expensive external ATE and relocates them into the IC itself, significantly reducing manufacturing and testing costs while maintaining measurement precision
Data Source
AI summary
An integrated circuit (IC) is provided. The IC includes: an RF transmitter configured to generate an RF signal when the IC has entered a test mode; an RF receiver configured to receive the RF signal in the test mode; and a computation unit having a plurality of processing units that are parallelized to perform a test procedure of the IC according to the received RF signal to determine one or more test results.