RF Receiver IF Amplifier Filtering for Low Noise and High Compression
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Solution Overview
Problem
Designing intermediate frequency (IF) amplifiers for ultra-wideband automotive radar receivers with deep sub-micron CMOS technologies poses challenges due to stringent requirements for low noise figure (NF) and high input 1-dB power compression point, exacerbated by noise from digital transistor switching in systems-on-a-chip (SoC) integrated circuits.
Innovation Solution
A two-stage low noise amplifier (LNA) with passive mixers and output amplifier sections, including intermediate frequency amplifiers with high-pass and low-pass filter circuitry, load resistors, and boost circuits, along with variable capacitors and resistors to achieve a low-noise RF receiver circuit capable of processing wideband signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital transistor switching is used in SoC integrated circuits, then functionality and integration are improved, but power supply noise increases
Solution Approach 1:
The patent segments the amplifier circuit into multiple stages with distinct functions: a first amplifier stage optimized for low noise performance and a second amplifier stage optimized for driving the mixer. This segmentation allows each stage to be independently optimized, with the first stage providing low noise gain and the second stage providing buffering, thereby achieving low noise figure while being integrated with noisy digital circuits.
Solution Approach 2:
The patent introduces an intermediate buffer stage between the low noise amplifier and the mixer. This intermediary stage acts as a mediator that isolates the sensitive low noise amplifier from the noisy digital circuits and the loading effects of the mixer, allowing the LNA to maintain its low noise performance while driving the mixer effectively.
2Object-affected harmful factors
If low noise figure is improved, then noise performance is enhanced, but input 1-dB power compression point may be reduced
Solution Approach 1:
The patent divides the amplification function into two stages: the first stage is optimized for low noise figure with appropriate biasing and transistor sizing, while the second stage is optimized for power handling and driving capability. This segmentation allows the first stage to operate in a regime that minimizes noise while the second stage provides the necessary power headroom, achieving both low noise figure and high input 1-dB power compression point.
Solution Approach 2:
The patent applies different design qualities to different parts of the circuit: the first amplifier stage uses device sizing and biasing optimized for low noise (local quality for noise performance), while the second stage uses different optimization for power handling and drive capability. This local quality approach allows simultaneous optimization of both noise figure and power compression point in different parts of the same circuit.
Data Source
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AI summary
An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.