RF Inductor Wiring Architecture With Stepped Dummy Metal Layers

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Solution Overview

Problem

The addition of dummy metals under inductor devices in radio frequency integrated circuits (RFICs) affects the performance of the inductor devices, leading to poor yield and potential short-circuiting due to insufficient metal arrangement areas in the bottom metal layers.

Innovation Solution

The inductor device wiring architecture features dummy metals arranged in multiple layers under the inductor device, with progressively increasing arrangement areas away from the inductor, forming a stepped shape to minimize performance impact and ensure sufficient metal areas for chemical mechanical polishing, thereby improving yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy metals are added under the inductor device to increase metal arrangement area, then processing quality and product yield are improved, but performance of the inductor device deteriorates

Engineering Contradiction:
Improveprocessing qualityVSAvoidinductor device performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The dummy metals are segmented into multiple metal layers (at least two layers) with different arrangement areas. Each layer is positioned at different distances from the inductor device, creating a graduated structure that reduces overall impact on inductor performance while collectively providing sufficient metal arrangement area for processing quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different metal layers have different local qualities in terms of dummy metal arrangement area. The first metal layer has a smaller arrangement area closer to the inductor device, while the second metal layer has a larger arrangement area farther from the inductor device. This local variation optimizes both inductor performance and processing quality.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If dummy metals are placed close to the inductor device to maximize metal arrangement area utilization, then processing quality is improved, but adverse effects on inductor device performance increase

Engineering Contradiction:
Improvemetal arrangement areaVSAvoidadverse effects on inductor device
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The solution transitions from a single-plane dummy metal arrangement to a multi-layer vertical arrangement. By utilizing the vertical dimension (different metal layers), the patent achieves sufficient total metal arrangement area while distributing dummy metals at different distances from the inductor device, thereby reducing harmful effects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dummy metals are preliminarily arranged in a graduated manner across multiple layers before the actual inductor device fabrication is completed. This preliminary strategic placement ensures that sufficient metal area is available for processing while minimizing performance impact from the outset.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12354954B2Inductor device wiring architecture, integrated circuit, and communications device
Publication Date: 2025.07.08 HUAWEI TECH CO LTD
  • US12354954B2 patent drawing
  • US12354954B2 patent drawing
  • US12354954B2 patent drawing

AI summary

Embodiments of this application disclose an inductor device wiring architecture, including an inductor device and a plurality of dummy metals located under the inductor device. The plurality of dummy metals are arranged in a plurality of metal layers. Each of the plurality of metal layers corresponds to some of the plurality of dummy metals. Arrangement areas of dummy metals corresponding to at least two of the plurality of metal layers progressively increase in a direction away from the inductor device. In the inductor device wiring architecture, adverse effects on performance of the inductor device can be reduced, and a product yield can be increased. The embodiments of this application further disclose an integrated circuit and a communications device.