Surface-Passivated High-Resistive Silicon Wafer for RF-IPDs
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Solution Overview
Problem
High-resistivity silicon substrates for RF-IPDs face issues with parasitic surface conduction due to charge trapping at the silicon-dielectric interface, leading to increased RF signal losses and reduced performance of inductors and filters.
Innovation Solution
A method involving mechanical sub-surface damage creation through processes like slicing, lapping, and grinding, followed by chemical-mechanical polishing to preserve a lattice damage zone that suppresses parasitic surface conduction, combined with optional polysilicon layer deposition to enhance passivation, reducing RF signal losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If heavy implantation with neutral species (argon, silicon, neutrons, or protons) is used to suppress parasitic surface conduction, then RF signal losses are reduced, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent extracts the harmful parasitic surface conduction by removing the damaged surface layer through chemical-mechanical polishing, eliminating the need for complex implantation processes. The damaged layer containing trapped charges is physically removed, leaving a clean interface that prevents parasitic channel formation.
Solution Approach 2:
The patent uses a disposable damaged surface layer that is intentionally created and then removed. This sacrificial layer approach replaces expensive and complex implantation processes with a simple mechanical removal step, significantly reducing manufacturing cost and process complexity.
2Loss of energy
If amorphous polysilicon layers are deposited on HRS substrates to suppress parasitic conduction, then RF performance is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
Instead of adding polysilicon layers, the patent extracts the problem source by removing the damaged surface layer through chemical-mechanical polishing. This extraction approach eliminates parasitic conduction without requiring additional material deposition steps, simplifying the manufacturing process.
Solution Approach 2:
The patent employs a sacrificial damaged surface layer that is created during slicing and lapping, then removed through polishing. This disposable layer approach replaces expensive polysilicon deposition with a cost-effective mechanical removal process.
3Manufacturing precision
If the damaged surface layer is completely removed through aggressive polishing, then a clean interface is achieved, but the parasitic conduction suppression effect is lost
Solution Approach 1:
The patent applies local quality by creating a controlled damaged layer specifically at the surface interface through slicing and lapping, then selectively removing it through polishing. The bulk substrate remains intact with high quality, while the surface layer is modified to eliminate parasitic conduction pathways.
Solution Approach 2:
The patent uses partial action by removing only the necessary portion of the damaged surface layer through controlled polishing, rather than completely removing all damaged material. This partial removal is sufficient to eliminate parasitic conduction while preserving the beneficial charge trapping effect near the interface.
4Loss of energy
If mechanical sub-surface damage is created through slicing and lapping, then parasitic conduction is suppressed, but surface quality deteriorates
Solution Approach 1:
The patent segments the surface treatment into two distinct stages: first creating controlled damage through slicing and lapping to suppress parasitic conduction, then separately applying chemical-mechanical polishing to restore surface quality. This segmentation allows both objectives to be achieved independently.
Solution Approach 2:
The patent performs preliminary damage creation through slicing and lapping before final surface finishing. The damaged layer is intentionally created as a preliminary step that is subsequently removed or modified through polishing, ensuring both parasitic suppression and surface quality are achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces RF signal losses and enhances the performance of RF-IPDs by suppressing parasitic surface conduction, achieving improved Q-factors and transmission line attenuation across a wide frequency range.
Implementation Method 1
charges trapped at the silicon - dielectric interface or within the dielectric layer itself can create accumulation or inversion layers, which enable parasitic surface conduction channels to be generated
Implementation Method 2
chemical-mechanical polishing to preserve a lattice damage zone
Implementation Method 3
mechanical sub-surface damage creation through processes like slicing, lapping, and grinding
Data Source
Figure 0~1c
Figure 2
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AI summary
The application relates to a manufacture method (200) of a surface-passivated high-resistivity silicon wafer (100) for a radio frequency integrated passive device. The method comprises a step of slicing (210) the high-resistivity silicon wafer from a grown high-resistivity silicon. The method further comprises a step of thinning (220, 230, 240) the sliced silicon wafer from a front side (122) of the silicon wafer for incorporating a sub-surface crystal lattice damage into the silicon wafer to cause a suppression of a parasitic surface conduction so that the front side of the silicon wafer comprises a fractured silicon comprised lattice damage zone (120a, 120b, 121, 124, 126) above a bulk silicon comprised bulk zone (110). The method further comprises a step of controlled polishing (250, 260, 272, 274) the front side of the thinned silicon wafer for removing a part (120a) of the fractured silicon so that a preserved part (120b, 121, 124, 126) of the fractured silicon establishes the polished front surface (122). The method further comprises a step of depositing (276) a polysilicon layer (130) on a top of the polished front surface comprising the preserved part of the fractured silicon for enhancing the suppression of the parasitic surface conduction that causes a reduction of radio frequency loss before the deposited polysilicon layer above the preserved part of fractured silicon is polished for providing surface quality compatible with a manufacture of the radio frequency integrated passive device.