RF Random Bit Generator Using Jittered Sampling for Low-Power RFID
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Solution Overview
Problem
Current random number generators for RFID tags consume excessive power, making them unsuitable for ultra-low power applications due to their high current consumption and requirement for wide band noise sources and amplifiers.
Innovation Solution
A true random number generator that utilizes a jittered clock signal with a frequency less than the received RF signal, coupled with a sample-and-hold circuit and noise buffer, to generate a random bit stream, reducing power consumption by using the received RF signal as both a power source and oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal noise amplification is used to generate random numbers, then true random numbers are produced, but power consumption increases due to wide band noise sources and amplifiers
Solution Approach 1:
The patent changes the fundamental parameter of randomness generation from thermal noise amplification to jitter-based sampling. By using a jittered clock signal to sample a stable oscillator output, the system achieves true randomness without requiring wide band noise sources and amplifiers, thereby dramatically reducing power consumption while maintaining random number quality
Solution Approach 2:
The patent extracts only the necessary component for randomness generation (the jittered clock signal) from the thermal noise amplification process. Instead of amplifying wide band noise, the system uses a narrow-band oscillator sampled by a jittered clock, removing the power-consuming wide band noise source and amplifier components
2Reliability
If a 1 GHz ring oscillator is used for random number generation, then random bits are produced, but current consumption becomes too high for RFID tags
Solution Approach 1:
The patent uses partial action by employing a low frequency oscillator (e.g., 1 MHz) instead of a high frequency oscillator (1 GHz). The jittered clock samples the oscillator at intervals, and the randomness comes from the jitter variability rather than the oscillator frequency, allowing much lower power consumption while still generating sufficient entropy for random bit production
Solution Approach 2:
The patent changes the oscillator frequency parameter from 1 GHz to a much lower frequency (e.g., 1 MHz), reducing current consumption by a factor of 1000. The randomness is maintained through the jittered sampling mechanism rather than relying on high frequency oscillation, achieving the same functional result with dramatically reduced power
3Reliability
If a jittered low frequency oscillator is used with a high frequency oscillator, then a random bit stream is output, but device complexity increases
Solution Approach 1:
The patent makes the received RF signal serve multiple functions: it provides both the power supply (through rectification and capacitor charging) and the oscillator signal for random number generation. This eliminates the need for separate power management and oscillator circuits, reducing device complexity while maintaining random bit stream output capability
Solution Approach 2:
The patent merges the power supply function and oscillator function into a single received RF signal. The RF signal is rectified to charge a capacitor for power, and the same RF signal is used as the high frequency oscillator input, combining two essential functions into one signal source and reducing overall circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces power consumption while maintaining randomness, ensuring that the probability of generating '1' and '0' bits is equal, thus addressing the power efficiency issues in RFID tag random number generation.
Implementation Method 1
A jittered clock signal source is coupled to the sample-and-hold circuit, frequency of the jittered clock signal being less than frequency of the received RF signal
Implementation Method 2
A sample-and-hold circuit is coupled to the RF signal source
Implementation Method 3
A noise buffer is coupled to the system clock for adding jitter to the clock signal to generate a jittered clock signal
Implementation Method 4
a received RF signal source
Data Source
AI summary
A random number generator generates a string of random bits from a received RF signal source. A sample-and-hold circuit is coupled to the received RF signal source. The RF signal is sampled by a jittered clock signal from a source coupled to the sample-and-hold circuit. The frequency of the jittered clock signal is less than frequency of the received RF signal. The random number appears at the output of the sample-and-hold circuit.