Programmable RF Mixer Clock Divider With Switchable HRM Loop
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Solution Overview
Problem
Conventional clock divider circuits in RF transceivers suffer from increased loading, power inefficiency, and phase noise due to the inclusion of multiple divider circuits for generating different frequency clock signals, and harmonic rejection mixers (HRMs) consume excessive power when not needed, leading to reduced operating time from battery power.
Innovation Solution
A programmable divider circuit with two separate clock loops, one for non-HRM phases and one for HRM phases, allowing the HRM loop to be disabled when not needed, reducing power consumption and enabling synchronization between loops to align phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple divider circuits are included to generate different frequency clock signals, then frequency versatility is improved, but power consumption increases and phase noise degrades
Solution Approach 1:
The patent merges multiple divider circuits into a single shared divider circuit that can be dynamically configured to provide different division ratios. This is achieved by using a common divider circuit with reconfigurable feedback paths, allowing the same hardware to serve multiple frequency generation needs without requiring separate dedicated divider circuits for each frequency, thereby reducing overall power consumption while maintaining frequency versatility.
Solution Approach 2:
The patent implements dynamic reconfiguration of the divider circuit's division ratio based on operational requirements. The feedback path is dynamically adjusted to change the division ratio, allowing the system to adapt to different frequency needs without switching between multiple static divider circuits. This dynamic approach ensures that only the necessary circuitry is active at any given time, optimizing power efficiency.
2Adaptability or versatility
If multiple divider circuits are included to generate different frequency clock signals, then frequency versatility is improved, but phase noise increases
Solution Approach 1:
The patent merges multiple divider circuits into a single shared divider circuit with reconfigurable feedback paths. This consolidation reduces the number of active circuits generating phase noise, as only one divider circuit operates at a time rather than multiple circuits being simultaneously active. The shared architecture minimizes cumulative phase noise while maintaining the ability to generate multiple frequency outputs.
3Reliability
If HRM loop is continuously active to support harmonic rejection mixer operations, then HRM functionality is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic enabling and disabling of the HRM loop based on operational requirements. The HRM loop is activated only when harmonic rejection functionality is needed and deactivated when not required, allowing the system to maintain reliable HRM functionality when needed while minimizing power consumption during normal operation. This on-demand activation approach ensures that the HRM loop does not continuously consume power.
4Adaptability or versatility
If multiple divider circuits are used, then clock signal generation flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple divider circuits into a single shared divider circuit with reconfigurable feedback paths. This consolidation reduces the total number of circuits required, simplifying the overall device architecture. The reconfigurable feedback mechanism provides the necessary flexibility for generating different frequency outputs without requiring separate dedicated circuits for each frequency, thereby reducing device complexity while maintaining generation flexibility.
Solution Approach 2:
The patent implements a universal divider circuit that can perform multiple functions by dynamically reconfiguring its feedback path. This single circuit serves the role of multiple dedicated divider circuits, providing different division ratios as needed. The multi-functional design reduces device complexity by eliminating redundant circuits while maintaining the flexibility to generate various clock signal frequencies.
Data Source
AI summary
This disclosure provides systems, methods, and devices for wireless communications that support configurable clock dividers for mixer operation in a radio frequency front end (RFFE). In a first aspect, an apparatus for wireless communications includes a first clock loop comprising a first plurality of latches generating a first plurality of clock signals with a corresponding first plurality of phases; and a second clock loop comprising a second plurality of latches generating a second plurality of clock signals with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal. Other aspects and features are also claimed and described.