RF MOS Switch Unit Cell Layout for Low Insertion Loss
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Solution Overview
Problem
Existing RF MOS switches with a comb-type layout suffer from high losses due to inadequate substrate impedance and difficult source and drain connections, limiting scalability and increasing electrical resistance.
Innovation Solution
A semiconductor device with a layout comprising rectangular unit cells, each divided by a cross-shaped gate into four corner regions, featuring source and drain regions in opposite corners, and connection members that extend over the gate, source, and drain to provide electrical connections, including trench isolation to improve impedance and reduce capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a comb-type layout is used for RF MOS switch, then the device structure is simple and easy to manufacture, but the insertion losses are relatively high due to inadequate substrate impedance and difficult source and drain connections
Solution Approach 1:
The gate is divided into multiple fingers that are interspersed with source and drain regions, creating a segmented comb-type structure. This segmentation increases the effective gate width and improves substrate impedance while maintaining ease of manufacture through standard photolithography patterning processes.
Solution Approach 2:
The patent introduces vertical stacking of metal interconnect layers with multiple vias to connect source and drain regions. This dimensional transition from 2D planar connections to 3D vertical interconnections reduces the horizontal connection length and electrical resistance, thereby reducing insertion losses while keeping the manufacturing process compatible with standard CMOS technology.
2Reliability
If deep trench isolation is used to surround the device, then isolation is improved, but substrate impedance within the device is not affected and losses remain high
Solution Approach 1:
The patent applies deep trench isolation selectively at the device periphery to provide electrical isolation, while intentionally leaving the central device region without trench isolation. This local differentiation allows the peripheral isolation to maintain reliability while the central region maintains low impedance and low loss characteristics, resolving the contradiction between isolation and loss reduction.
3Ease of operation
If connections to source and drain regions are made through a series of vias, then electrical connections are provided, but the connections have relatively high electrical resistance
Solution Approach 1:
The patent combines multiple metal interconnect layers with vertical vias to create thick, low-resistance connection paths to source and drain regions. By merging multiple conductive layers and optimizing via dimensions, the effective cross-sectional area of the connections is increased, reducing electrical resistance and energy loss while maintaining ease of electrical connection.
4Quantity of substance
If scaling is achieved by adding additional fingers to the comb, then device capacity increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs the unit cell with universal connection points and standardized via patterns that can be replicated and tiled to scale the device. This universal design allows device capacity to be increased by simply adding more identical unit cells in parallel, rather than redesigning the entire structure, thereby increasing capacity while minimizing the increase in manufacturing complexity.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells. Each unit cell includes a gate that divides the unit cell into four corner regions. Each unit cell also includes a source comprising first and second source regions located in respective opposite corner regions of the unit cell. Each unit cell further includes a drain comprising first and second drain regions located in respective opposite corner regions of the unit cell. Each unit cell also includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the gate, source and drain,