RF Semiconductor Package Carrier With Grounded Signal Routing

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Solution Overview

Problem

Existing semiconductor packaging methods, such as flip-chip bonding and wire bonding, are either costly and inconvenient or fail to provide adequate performance for high-frequency radio frequency (RF) applications.

Innovation Solution

A semiconductor package design that includes a carrier with conductive layers on either side, where the semiconductor die is flip-chip mounted on one side and electrically connected to the conductive layers, allowing for efficient RF signal transmission and robust grounding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flip-chip bonding is used to attach semiconductor die to board, then connection reliability is improved, but equipment cost and complexity increase

Engineering Contradiction:
Improveconnection reliabilityVSAvoidequipment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a carrier as an intermediary component between the semiconductor die and the board. The carrier includes conductive layers and vias that provide electrical connections, allowing the die to be mounted on the carrier rather than directly on the board. This intermediary structure enables reliable electrical connections while using simpler, more accessible mounting equipment.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If wire bond techniques are used, then equipment cost is reduced, but RF performance deteriorates

Engineering Contradiction:
Improveequipment simplicityVSAvoidRF performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the electrical connection path into multiple controlled components: conductive layers on the carrier, vias through the carrier, and trace routing. This segmentation allows each component to be optimized for RF performance - the conductive layers provide low-inductance ground planes, the vias provide controlled impedance transitions, and the overall structure minimizes signal loss while using simpler wire bonding equipment.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If conventional packaging is used, then manufacturing simplicity is maintained, but RF signal transmission performance deteriorates

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidRF signal transmission
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes key electrical parameters of the packaging structure - the conductive layers are configured to provide low inductance and controlled impedance, the vias are designed with specific dimensions and spacing for optimal RF performance, and the overall carrier structure is optimized for signal integrity. These parameter changes enable high-frequency signal transmission while maintaining compatibility with standard manufacturing processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed package design enhances RF performance by providing a robust ground connection and efficient signal transmission, making it suitable for high-frequency applications while reducing the need for expensive alignment equipment.

Implementation Method 1

The vias can receive electrical ground from the second conductive layer

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the first conductive layer carries RF signals

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

the carrier is attached to the PCB by an epoxy that is both thermally and electrically conductive

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12283555B2Semiconductor packages
Publication Date: 2025.04.22 ANALOG DEVICES INT UNLTD CO
  • US12283555B2 patent drawing
  • US12283555B2 patent drawing
  • US12283555B2 patent drawing

AI summary

A package is disclosed. The package includes a carrier that comprises a first conductive layer on a first side and a second conductive layer on a second side opposite the first side. The first conductive layer comprises wire bonding pads. The package also includes a semiconductor die that is flip chip mounted on the first side of the carrier.