Integrated RF Passives With Thin Dielectrics for Dense Coupling

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Solution Overview

Problem

Current semiconductor packaging designs limit the optimization of electrical properties of inductors and capacitors, making it difficult to achieve high coupling factors and capacitance density, which increases system size and cost, and reduces the maximum operating frequency in RF and power delivery applications.

Innovation Solution

The use of a semi-additive manufacturing process to form integrated transformers and capacitors with reduced dielectric spacer thickness, allowing for closer spacing of conductive loops and thinner dielectric layers, thereby increasing coupling factors and capacitance density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional packaging design rules are used with minimum allowable spacing between conductive lines, then manufacturing is simplified, but coupling factors cannot exceed 0.5 and require large area and many layers

Engineering Contradiction:
Improvecoupling factorVSAvoidpackage area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent changes the dielectric thickness parameter from traditional thick layers (20 μm or greater) to thin dielectric layers (less than 20 μm, preferably 1-10 μm). This parameter change enables coupling factors greater than 0.5 while reducing the area required for transformers, resolving the contradiction between achieving high coupling and minimizing package area.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If thick dielectric layers (20 μm or greater) are used for capacitor plates, then manufacturing is easier, but capacitance per unit area is small requiring larger package size or additional discrete capacitors

Engineering Contradiction:
Improvedielectric layer fabricationVSAvoidcapacitance density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent changes the dielectric thickness parameter from thick (20 μm or greater) to thin (less than 20 μm, preferably 1-10 μm). Since capacitance is inversely proportional to dielectric thickness, this parameter change dramatically increases capacitance density, allowing desired capacitance values to be achieved in smaller areas without additional discrete capacitors.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If additional discrete capacitors are used to achieve desired capacitance, then capacitance requirements are met, but routing parasitics increase and maximum operating frequency is reduced

Engineering Contradiction:
ImprovecapacitanceVSAvoidmaximum operating frequency
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent merges the capacitor fabrication process with the existing packaging substrate layers, integrating capacitors directly into the package rather than using discrete components. This integration eliminates additional routing parasitics associated with discrete capacitors, thereby maintaining or improving the maximum operating frequency while meeting capacitance requirements.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of manufacture

If minimum allowable spacing between conductive lines is used, then manufacturing is simplified, but tightly coupled inductors cannot be achieved in small area

Engineering Contradiction:
Improveconductive line spacingVSAvoidcoupling factor
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the dielectric thickness parameter to thin layers (less than 20 μm), which enables tight coupling between conductive lines without requiring minimum spacing constraints. This allows inductors with coupling factors greater than 0.5 to be fabricated in small areas using standard manufacturing processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12002745B2High performance integrated RF passives using dual lithography process
Publication Date: 2024.06.04 INTEL CORP
  • US12002745B2 patent drawing
  • US12002745B2 patent drawing
  • US12002745B2 patent drawing

AI summary

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.