Stacked Complementary RF Power Amplifier Voltage Stress Reduction
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Solution Overview
Problem
Prior art power amplifiers suffer from significant second-order distortion and reliability issues due to high drain-to-source voltage, which limits their full output capacity and requires stringent power supply voltage constraints.
Innovation Solution
A power amplifier design featuring a stacked complementary common-source amplifier pair with a PMOS and NMOS transistor configuration, utilizing coupling networks and inductors to equalize drain voltages and reduce peak voltage stress, along with an output combiner to minimize second-order distortion and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single common-source amplifier is used, then the output capacity is high, but the second-order distortion is significant and the drain-to-source voltage stress is high
Solution Approach 1:
The patent divides a single common-source amplifier into two stacked common-source amplifiers (first and second common-source amplifiers with PMOS and NMOS transistors respectively). Each amplifier handles a portion of the signal, reducing the voltage stress on individual transistors while maintaining overall output capacity through the stacking configuration.
Solution Approach 2:
The patent transitions from a single-stage amplifier to a two-stage stacked amplifier configuration, adding a vertical dimension to the circuit architecture. This stacking approach distributes the voltage burden across multiple devices in series, reducing peak stress on each transistor while preserving the amplifier's overall gain and output capability.
2Device complexity
If a single common-source amplifier is used, then the circuit is simple, but the second-order distortion is significant
Solution Approach 1:
The patent segments the amplification function into two separate common-source amplifiers operating in parallel at the signal level. The first common-source amplifier and second common-source amplifier each contribute to the overall signal amplification, and their combined output through the coupling network achieves distortion cancellation while maintaining a relatively simple circuit topology.
3Productivity
If high power supply voltage is used to increase output capacity, then the full output capacity increases, but the transistor stress increases and reliability decreases
Solution Approach 1:
The patent segments the voltage burden across two stacked amplifiers, where each amplifier's transistor experiences reduced peak drain-to-source voltage compared to a single amplifier operating at the same total supply voltage. This segmentation allows the system to achieve high output capacity without subjecting individual transistors to excessive stress.
Solution Approach 2:
The patent changes the voltage distribution parameters by introducing a stacked configuration with intermediate voltage nodes. The first DC node and second DC node create separate voltage domains, allowing each transistor to operate within safer voltage limits while the overall system maintains high output capacity through the combined effect of both amplifiers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively alleviates second-order distortion and reduces transistor stress, allowing for higher power supply voltages and maintaining the overall output capacity while improving reliability.
Implementation Method 1
a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage
Implementation Method 2
a first inductor configured to couple the first drain node to a first DC node; a second inductor configured to couple the second drain node to a second DC node; a third inductor configured to be inductively coupled with the first inductor; a fourth inductor configured to be inductively coupled with the second inductor
Implementation Method 3
a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage
Implementation Method 4
an output combiner configured to output an output voltage in accordance with a combination of the a voltage of the third inductor and a voltage of the fourth inductor
Data Source
AI summary
An apparatus having a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage at a first gate node and a second gate node, respectively; a stacked complementary common-source amplifier pair including a first common-source amplifier and a second common-source amplifier configured to receive the first gate voltage and the second gate voltage and output a first drain voltage and a second drain voltage at a first drain node and a second drain node, respectively; a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage. A first inductor and second inductor couple the first and second drain nodes to a first and second DC node, respectively. Third and fourth inductors are coupled to the first and second inductor.