RF Power Control Circuit With Feedback Against Channel Length Modulation

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Solution Overview

Problem

The channel length modulation effect in existing power control circuits for radio frequency power amplifiers affects the performance by introducing deviations in bias current control, leading to reduced control accuracy and output power management.

Innovation Solution

A power control circuit is designed with a radio frequency signal path and a negative feedback loop, utilizing NMOS transistors and a differential amplifier to maintain equal drain and gate voltages, ensuring the transistors operate in saturation regions, thus eliminating channel length modulation effects and improving control accuracy without interfering with the radio frequency signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a power control circuit is used to control the output power of the radio frequency power amplifier, then the output power control is achieved, but the channel length modulation effect affects the performance and reduces control accuracy

Engineering Contradiction:
Improvecontrol accuracyVSAvoidamplifier performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The circuit is divided into separate RF signal path (first NMOS transistor) and control path (third and fourth NMOS transistors), allowing independent optimization of each path to avoid mutual interference and eliminate channel length modulation effects from the control path affecting the RF path

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The differential amplifier acts as an intermediary that compares the drain voltage of the fourth NMOS transistor with a reference voltage and adjusts the gate voltage accordingly, enabling precise control of the first NMOS transistor while compensating for channel length modulation effects

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate bias voltage is controlled to manage output power, then power control function is achieved, but channel length modulation introduces deviations in bias current control

Engineering Contradiction:
Improvepower control functionVSAvoidbias current control accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The negative feedback loop using the differential amplifier continuously monitors and adjusts the gate voltage of the first NMOS transistor based on the actual output, compensating for channel length modulation effects and maintaining accurate bias current control across varying operating conditions

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit dynamically adjusts the gate voltage parameter of the first NMOS transistor through the control path, changing this parameter in response to feedback signals to maintain optimal bias current despite channel length modulation effects

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11881820B2Power control circuit
Publication Date: 2024.01.23 GUANGZHOU HUIZHI MICROELECTRONICS
  • US11881820B2 patent drawing
  • US11881820B2 patent drawing
  • US11881820B2 patent drawing

AI summary

A power control circuit includes a negative feedback loop, and a radio frequency signal path including a first NMOS transistor having a gate configured as a radio frequency signal input end, a drain connected with a source of a second NMOS transistor, and a source connected with a ground terminal. A drain of the second NMOS transistor is configured as a radio frequency signal output end and connected with a first voltage source. The negative feedback loop includes a third NMOS transistor having a gate connected with an output end of a differential amplifier, a source connected with the ground terminal, and a drain connected with a source of a fourth NMOS transistor having a gate connected with a reverse input end of the differential amplifier and with a second voltage source, and a drain connected with a forward input end and a first bias current source.