RF Pulsing Etching for Spacer Damage-Free Semiconductor Patterning
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Solution Overview
Problem
The semiconductor industry faces challenges in patterning semiconductor devices due to spacer damage during etching processes, which can lead to critical dimension uniformity issues and device failures, especially as geometry sizes decrease and overlay shifts become more problematic.
Innovation Solution
A method that simultaneously performs etching and protective coating deposition using RF power pulsing, where etching occurs when RF power is on and polymer deposition occurs when it is off, to minimize spacer damage and maintain critical dimension uniformity, allowing for a larger overlay and clearance window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used, then manufacturing simplicity is maintained, but spacer damage occurs leading to poor critical dimension uniformity
Solution Approach 1:
The patent combines etching and protective coating deposition into a single integrated process step. The protective coating is deposited during the etching process itself, merging two previously separate operations (etching followed by separate coating deposition) into one simultaneous process, thereby improving critical dimension uniformity without proportionally increasing process complexity
Solution Approach 2:
The protective coating is applied in advance during the etching process before the actual etching damage can occur. This preliminary protective action prevents spacer damage during etching, ensuring better critical dimension uniformity is achieved from the outset rather than requiring corrective steps later
2Manufacturing precision
If overlay shift margin is reduced to prevent spacer damage, then manufacturing precision improves, but productivity decreases due to stricter process control
Solution Approach 1:
The protective coating serves as a cushioning layer applied beforehand during the etching process. This coating absorbs or mitigates the harmful effects of etching on the spacers, providing a buffer that allows for larger overlay shifts without causing spacer damage, thereby maintaining productivity while ensuring precision
3Loss of time
If separate etching and coating deposition steps are used, then process control is simplified, but time consumption increases
Solution Approach 1:
The patent merges etching and protective coating deposition into a single simultaneous process step using RF power pulsing. This integration eliminates the need for separate sequential steps, reducing total process cycle time while the RF power pulsing mechanism provides automated process control that manages the complexity of coordinating both functions
4Reliability
If RF power pulsing is used for simultaneous etching and coating deposition, then spacer damage is reduced, but energy consumption increases
Solution Approach 1:
The patent employs periodic RF power pulsing to alternately perform etching and protective coating deposition. This periodic action allows the system to switch between etching mode and coating mode, reducing net energy consumption compared to continuous high-power operation while still achieving the protective effect that improves device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces spacer damage and maintains critical dimension uniformity, even with larger overlay errors, thereby improving the reliability and performance of semiconductor devices by allowing for a more relaxed overlay shift margin.
Implementation Method 1
extending the openings into the bottom layer. The extending is performed in a Radio Frequency (RF) power pulsing chamber via a plurality of pulsing cycles, wherein each pulsing cycle includes an etching step performed while the RF power is turned on
Implementation Method 2
a polymer deposition step performed while the RF power is turned off. The polymer deposition step deposits a polymer layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features
Data Source
AI summary
A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.