RF Redistribution Layer Inductance for Lower Switch Insertion Loss
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Solution Overview
Problem
Existing radio-frequency (RF) switches face challenges due to parasitic capacitance, which leads to increased insertion loss and higher implementation costs, particularly in flip chip devices where external inductors are used to compensate for this capacitance.
Innovation Solution
Implementing a redistribution layer (RDL) inductance within the semiconductor chip to provide a selected inductance that compensates for parasitic capacitance, reducing insertion loss and eliminating the need for external inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external inductors are used to compensate for parasitic capacitance in flip chip devices, then the parasitic capacitance is compensated, but the device complexity and implementation cost increase
Solution Approach 1:
The patent merges the inductor function with the existing redistribution layer structure by configuring specific trace patterns (such as spiral or meander patterns) within the RDL. This integration eliminates the need for separate external inductor components while maintaining the parasitic capacitance compensation function, thereby reducing device complexity and implementation cost.
Solution Approach 2:
The redistribution layer is designed to serve multiple functions: it provides electrical connections between pads and circuit blocks, and simultaneously functions as an inductor to compensate for parasitic capacitance. This multi-functionality approach allows the same structural element to fulfill both interconnection and impedance compensation roles, reducing overall device complexity.
2Reliability
If external inductors are used to compensate for parasitic capacitance, then the parasitic capacitance is compensated, but the implementation cost increases
Solution Approach 1:
The inductor function is combined with the redistribution layer traces, eliminating the need for separate external inductor components. This integration reduces the total component count and assembly steps, thereby reducing implementation cost while maintaining parasitic capacitance compensation capability.
Solution Approach 2:
The redistribution layer structure is designed to inherently provide inductance through its trace geometry (spiral, meander, or optimized straight traces). The RDL serves itself by using its own structural characteristics to provide the compensation function, eliminating the need for additional dedicated compensation components and reducing manufacturing cost.
3Ease of operation
If traditional redistribution layer design is used, then the electrical connections are provided, but the insertion loss is high due to uncompensated parasitic capacitance
Solution Approach 1:
The patent applies local quality optimization by designing specific trace patterns (such as spiral or meander patterns) in critical signal paths where parasitic capacitance compensation is most needed. The RDL traces are configured with specific geometries in these local regions to provide inductance that compensates for the parasitic capacitance of switching devices, thereby reducing insertion loss in those specific signal paths while maintaining overall electrical connection functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RDL inductance reduces insertion loss by approximately 0.2 dB and achieves a high Q value, thereby improving the efficiency and reducing costs by integrating the inductance within the chip.
Implementation Method 1
The signal path is configured to provide a selected inductance. The selected inductance can compensate for some or all of parasitic capacitance associated with the switching circuit.
Implementation Method 2
The selected inductance can compensate for some or all of parasitic capacitance associated with the switching circuit.
Data Source
AI summary
In some embodiments, a semiconductor chip device can be manufactured by a method that includes forming a plurality of layers including a redistribution layer, such that the redistribution layer has a signal path that provides a selected electrical property with a first end electrically connected to a first node and a second end electrically connected to a second node. The method can further include coupling a semiconductor substrate with a circuit to the plurality of layers, such that the first node is electrically connected to the circuit and the second node is connectable to a location external to the semiconductor chip device.


