RF Receiver Dynamic Frequency Planning for Spur and Coupling Control

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Solution Overview

Problem

Integrated RF receivers face issues with unwanted signal coupling due to electrical or magnetic interactions between circuits, leading to signal distortion and artifacts, which traditional layout strategies and ground rings cannot completely eliminate.

Innovation Solution

The RF receiver employs a frequency planning algorithm within the TV tuner chip to dynamically adjust the clock synthesizer's frequency, reducing harmful coupling by avoiding frequency overlaps with desired channels and minimizing spur generation through fine increments in frequency adjustment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If integrated circuit technology is used to combine circuits on-chip, then cost is reduced, but unwanted signal coupling between circuits increases

Engineering Contradiction:
ImprovecostVSAvoidsignal coupling
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic frequency planning where the system continuously monitors for signal coupling artifacts and adjusts the frequency of the aggressor circuit in real-time to eliminate the coupling. This dynamic adjustment allows the integrated circuit to maintain cost benefits while adapting to changing coupling conditions to preserve signal integrity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the frequency parameter of the aggressor circuit dynamically based on detected coupling conditions. By adjusting the frequency away from values that cause harmful coupling, the system resolves the contradiction between integration benefits and coupling problems without requiring physical separation or additional shielding structures.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If traditional layout strategies and ground rings are used to reduce coupling, then some coupling is reduced, but harmful coupling effects cannot be completely eliminated

Engineering Contradiction:
Improvesignal couplingVSAvoidlayout complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent replaces physical/layout-based coupling reduction methods with a frequency-domain solution. Instead of relying on physical separation, ground rings, or complex layout strategies, the system uses dynamic frequency adjustment to eliminate coupling effects, thereby reducing layout complexity while achieving complete coupling elimination.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system monitors its own coupling conditions and automatically adjusts frequencies to eliminate harmful effects. This self-service approach allows the circuit to maintain simple layout while dynamically compensating for coupling issues that arise during operation.

Inventive Principle:
Principle #25Self-service

3Reliability

If frequency adjustment is used to reduce coupling, then signal integrity is improved, but additional control mechanisms are required

Engineering Contradiction:
Improvesignal integrityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the system monitors for coupling artifacts and uses this information to adjust the aggressor frequency. This closed-loop control improves signal integrity by continuously adapting to coupling conditions while keeping the control mechanism relatively simple through algorithmic frequency selection.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8666349B2Radio frequency (RF) receiver with dynamic frequency planning and method therefor
Publication Date: 2014.03.04 SILICON LABORATORIES INC
  • US8666349B2 patent drawing
  • US8666349B2 patent drawing
  • US8666349B2 patent drawing

AI summary

A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.