RF-SOI Trap-Rich Layer Doping for Back-Gate Effect Control
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Solution Overview
Problem
The back-gate effect in radio frequency silicon-on-insulator (RF-SOI) substrates, caused by parasitic surface conduction and parasitic gate electrodes, affects the performance of RF devices by inducing leakage currents and threshold voltage shifts, particularly in high-voltage switching transistors.
Innovation Solution
Implementing n-type and/or p-type doping in the trap-rich layer immediately below RF-SOI circuits, combined with through-box contacts to bias these regions independently, reduces the resistivity and enhances charge transfer rates, thereby mitigating back-gate effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trap-rich layer is introduced to reduce parasitic surface conduction, then RF device performance is improved, but back-gate effects are induced that cause leakage currents and threshold voltage shifts
Solution Approach 1:
The patent applies local quality by creating a doped region specifically in the trap-rich layer beneath RF circuits that require back-gate control, while leaving other regions undoped. This localized doping allows selective mitigation of back-gate effects only where needed, preserving the trap-rich layer's overall functionality for reducing parasitic surface conduction while adding targeted control capability for back-gate induced leakage currents and threshold voltage shifts.
Solution Approach 2:
The patent changes the electrical parameters of the trap-rich layer by introducing dopant atoms, which modifies the charge carrier concentration and electrical conductivity in the doped region. This parameter change enables the doped region to function as a back-gate control mechanism, counteracting the harmful back-gate effects while maintaining the trap-rich layer's primary function elsewhere.
2Power
If high voltages are applied to switching transistors, then switching capability is enhanced, but electric fields are induced in the BOX and trap-rich layers that couple to the bulk substrate and worsen back-gate effects
Solution Approach 1:
The patent introduces a doped region in the trap-rich layer as an intermediary structure between the BOX layer and the bulk substrate. This intermediary doped region acts as a controlled interface that manages the coupling of electric fields from high-voltage switching transistors to the bulk substrate, reducing unwanted back-gate effects while allowing the high-voltage switching capability to function properly.
3Speed
If the bulk substrate resistivity is reduced to improve charge transfer, then charge transfer rate increases, but parasitic surface conduction increases causing signal coupling
Solution Approach 1:
The patent applies local quality by creating a doped region with reduced resistivity specifically beneath RF circuits where improved charge transfer is needed, while maintaining high resistivity in the bulk substrate and trap-rich layer elsewhere. This localized approach enables enhanced charge transfer rate in critical areas without inducing parasitic surface conduction that would cause signal coupling between adjacent circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces back-gate effects by improving ON-state conduction and reducing OFF-state current leakage in RF-SOI circuits, maintaining independent operation of adjacent circuits without influencing each other.
Implementation Method 1
doping a region of a trap-rich layer that is immediately below the SOI circuit; based on the doping, reducing a resistivity of the region, thereby increasing a charge transfer rate of the region
Implementation Method 2
presence of the trap-rich layer (130) may produce a trap-rich effect that includes trapping of free charges (e.g., electrons, carriers) underneath the BOX layer (120), thereby preventing flow of current
Implementation Method 3
a thin layer of silicon (110, also referred to as SOI layer) overlying an insulating BOX layer (120, e.g., SiO2)
Data Source
AI summary
Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit/device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and/or junction fully contains a projection of a planar surface area of the first circuit and/or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit/device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.