RF SOI Switch Cavity Isolation Parasitic Coupling
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Solution Overview
Problem
Field effect transistors used in radio frequency applications face performance issues due to high parasitic capacitive coupling and signal distortion caused by source to drain leakage and substrate coupling, which affect insertion loss and linear characteristics.
Innovation Solution
An integrated circuit structure with a compound semiconductor substrate featuring a cavity below the transistor and isolation plugs on either side, reducing parasitic capacitive coupling by using a dielectric layer and shallow trench isolations to isolate the transistor from the substrate, and manufacturing methods involving shallow trench isolation and dielectric material formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional field effect transistor structure is used without substrate isolation, then the device complexity is low and manufacturing is simple, but parasitic capacitive coupling between source/drain and substrate increases, degrading RF performance
Solution Approach 1:
The patent extracts the transistor from direct contact with the substrate by forming a cavity beneath the transistor body. This separation removes the harmful parasitic capacitive coupling between the source/drain regions and the substrate, improving RF performance metrics such as insertion loss and linear characteristics while maintaining a manageable structural complexity through systematic fabrication processes
Solution Approach 2:
The patent introduces a vertical dimension by forming a cavity beneath the transistor, moving from a planar 2D structure to a 3D structure with depth. This vertical separation creates isolation between the transistor and substrate without requiring complex lateral modifications, effectively reducing parasitic coupling while keeping the manufacturing process relatively straightforward
2Reliability
If a cavity is formed below the transistor to reduce parasitic coupling, then parasitic capacitive coupling is reduced and RF performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary actions by forming the cavity structure early in the fabrication process, before final transistor assembly. The cavity is created through selective etching and isolation plug formation in subsequent steps, preparing the substrate structure in advance to accommodate the transistor and reduce parasitic coupling without complicating later manufacturing stages
Solution Approach 2:
The patent segments the substrate structure by forming isolated cavity regions separated by isolation plugs. This segmentation allows the cavity to be created using standard fabrication techniques applied to divided regions, making the manufacturing process more manageable while still achieving the overall goal of reducing parasitic capacitive coupling across the transistor structure
3Speed
If isolation plugs are added to separate cavities, then parasitic coupling is further reduced and switching speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces isolation plugs as intermediary elements between adjacent cavities. These plugs act as mediators that further reduce parasitic coupling paths while maintaining a structured and organized isolation scheme. The isolation plugs are formed through conventional shallow trench isolation processes, preventing excessive complexity from arising
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitive coupling, enhancing the performance of the integrated circuit by minimizing signal distortion and insertion loss, thereby improving switching speed and signal integrity.
Implementation Method 1
parasitic capacitive couplings between the source, drain of the transistor and the substrate are reduced
Implementation Method 2
By having a cavity located below the transistor, parasitic capacitive couplings between the source, drain of the transistor and the substrate are reduced
Data Source
AI summary
An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.