RF Silicon-on-Insulator Structure With Trap-Rich Interface Layer
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Solution Overview
Problem
Current methods for producing semiconductor-on-insulator (SOI) wafers for radio frequency (RF) devices face challenges in maintaining high resistivity levels, leading to parasitic power losses and harmonic distortion due to the formation of charge inversion or accumulation layers at the buried oxide/handle interface.
Innovation Solution
A multilayer structure comprising a high resistivity float zone silicon wafer with a trap rich layer and a dielectric layer is integrated into the SOI structure, which suppresses the formation of parasitic conduction layers and enhances RF performance by capturing free carriers at the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SOI wafer production methods are used, then manufacturing process is simpler, but parasitic conduction layers form at the buried oxide/handle interface causing RF performance degradation
Solution Approach 1:
A trap-rich layer is introduced as an intermediary between the high-resistivity handle wafer and the buried oxide layer. This intermediate layer captures free carriers and prevents the formation of parasitic conduction layers at the interface, thereby improving RF performance without requiring changes to the fundamental SOI structure
Solution Approach 2:
The patent employs a composite multilayer structure combining high-resistivity float zone silicon, trap-rich layer, and buried oxide layer. Each layer contributes specific properties: the handle wafer provides high resistivity, the trap-rich layer provides carrier trapping, and the oxide provides electrical isolation, together achieving superior RF performance
2Reliability
If high resistivity handle wafers are used, then RF performance is improved, but charge accumulation layers form at the interface causing harmonic distortion
Solution Approach 1:
The patent converts the potentially harmful charge accumulation at the interface into a beneficial effect by introducing a trap-rich layer that deliberately captures free carriers. This prevents the formation of parasitic conduction layers and reduces harmonic distortion, turning the interface charge issue into an opportunity for improved RF performance
3Stability of the object's composition
If float zone silicon with low oxygen content is used, then resistivity stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies precise parameter ranges for the float zone silicon handle wafer, including oxygen content between 1×10^15 to 1×10^17 atoms/cm³ and resistivity greater than 1000 ohm-cm. These controlled parameter changes ensure resistivity stability and prevent parasitic conduction layer formation while maintaining compatibility with standard manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves superior RF performance with reduced harmonic distortion and improved resistivity stability, enabling better device isolation and reduced RF losses, with second harmonic distortion values of better than −100 dBm.
Implementation Method 1
a trap rich layer in interfacial contact with the front surface of the single crystal silicon wafer handle substrate... suppresses the formation of parasitic conduction layers and enhances RF performance by capturing free carriers at the interface
Implementation Method 2
a dielectric layer in interfacial contact with the trap rich layer... enabling better device isolation and reduced RF losses
Data Source
AI summary
A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.