RF SOI Wafer Structure With Trap-Rich Layer for Parasitic Conduction
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Solution Overview
Problem
Current semiconductor-on-insulator (SOI) wafer manufacturing methods face challenges in achieving high resistivity levels necessary for superior radio frequency (RF) device performance, as they often result in parasitic power losses and device nonlinearity due to the formation of high conductivity charge inversion layers at the buried oxide/handle interface.
Innovation Solution
A multilayer structure comprising a high resistivity float zone silicon wafer handle substrate with a trap rich layer and a dielectric layer is integrated into the semiconductor-on-insulator structure, which suppresses the formation of parasitic conduction layers and maintains high resistivity even in the near-surface region, thereby enhancing RF device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SOI wafer manufacturing methods are used, then manufacturing simplicity is maintained, but parasitic conduction layers form at the buried oxide/handle interface reducing RF performance
Solution Approach 1:
An intermediate layer is introduced between the handle wafer and the buried oxide layer. This intermediate layer acts as a mediator that prevents the formation of parasitic conduction layers at the interface, thereby improving RF device performance without complicating the manufacturing process
Solution Approach 2:
The electrical parameters of the handle wafer are modified by introducing the intermediate layer, which changes the charge distribution and conductivity characteristics at the interface. This parameter change suppresses parasitic conduction while maintaining the structural integrity of the SOI wafer
2Reliability
If high resistivity is achieved in the handle wafer, then RF performance improves, but charge inversion layers form at the interface causing device nonlinearity
Solution Approach 1:
The intermediate layer serves as a buffer that decouples the high resistivity handle wafer from the buried oxide layer. This mediation prevents charge inversion while preserving the high resistivity characteristic necessary for stable RF performance
Solution Approach 2:
The intermediate layer introduces local quality variation at the interface region, creating a transition zone with different electrical properties. This localized modification prevents charge inversion without affecting the overall high resistivity of the handle wafer
Data Source
AI summary
A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.