Local Oscillator Frequency Integer Multiple for RF Spur Reduction
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Solution Overview
Problem
Modern RF transceivers face challenges in reducing spurs (digital commutation spurs) that interfere with analogue components, leading to poor signal-to-noise ratios due to the integration of digital and analogue circuitry, particularly in CMOS technology, where area constraints and process limitations make it difficult to isolate digital spurs effectively.
Innovation Solution
The solution involves generating a local oscillator signal such that any spurs from digital components are kept outside the intermediate frequency band by ensuring the local oscillator signal is an integer multiple of the digital clock frequency, allowing higher harmonics to be filtered out, thereby minimizing spur interference and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If digital and analogue modules are integrated on the same die, then area constraints are satisfied and manufacturing cost is reduced, but digital commutation spurs interfere with analogue signal processing leading to poor signal-to-noise ratio
Solution Approach 1:
The patent changes the frequency parameter of the local oscillator signal to be an integer multiple of the digital clock frequency. This parameter adjustment ensures that digital spurs are transposed to DC or fall outside the intermediate frequency band, resolving the contradiction by maintaining integration benefits while eliminating spur interference through frequency domain separation.
2Object-affected harmful factors
If isolation techniques such as separate power supplies or deep-N well isolation are used, then digital spur interference is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of using complex isolation structures, the patent changes the frequency parameter of the local oscillator signal. This simpler approach achieves spur reduction through frequency domain separation, avoiding the need for additional isolation hardware and reducing device complexity while maintaining effective spur rejection.
3Productivity
If digital clock frequency is increased to improve digital processing speed, then productivity is improved, but digital spurs fall within the intermediate frequency band causing more interference
Solution Approach 1:
The patent changes the relationship between local oscillator frequency and digital clock frequency by making the local oscillator frequency an integer multiple of the clock frequency. This allows higher digital clock frequencies to be used for improved processing speed while ensuring spurs are transposed to DC or fall outside the intermediate frequency band, thus resolving the contradiction between speed and interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the impact of digital spurs on the analogue components, enhancing the signal-to-noise ratio of the intermediate frequency signal by ensuring spurs are either transposed to DC or fall outside the filtered bandwidth, thus improving the overall performance of the RF transceiver.
Implementation Method 1
a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal
Implementation Method 2
allowing higher harmonics to be filtered out
Data Source
AI summary
Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.