RF Transistor Stack Gate Capacitor Topology for Higher Stack Heights
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Solution Overview
Problem
Existing amplifier circuits with stacked transistors face challenges in achieving practical realization of large stack heights due to decreasing capacitance values of gate capacitors approaching parasitic/stray capacitance levels, making it difficult to maintain desired voltage distribution across transistors, especially as the number of transistors increases.
Innovation Solution
The proposed solution involves a monolithically integrated circuit arrangement with a cascode configuration of transistors, where gate capacitors are coupled in specific configurations to maintain higher capacitance values, allowing for larger stack heights and desired RF voltage distribution across the transistors, by connecting at least one gate capacitor to a coupling capacitor and others to a reference voltage, thereby increasing the effective capacitance and preventing voltage stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of transistors in the stack increases to achieve higher output power, then the output power capability is improved, but the gate capacitor capacitance values decrease to levels approaching parasitic/stray capacitance, making practical realization difficult
Solution Approach 1:
The patent combines multiple gate capacitors in parallel for transistors closer to the output of the stack. Specifically, the gate capacitors are merged in groups where capacitors for transistors at similar positions are connected in parallel, thereby increasing the effective capacitance values to practical levels while maintaining the desired voltage distribution across the transistor stack.
2Manufacturing precision
If gate capacitor capacitance values are decreased to maintain voltage distribution in larger stacks, then the voltage distribution is improved, but the capacitance values approach parasitic/stray capacitance levels, rendering practical realization challenging
Solution Approach 1:
The patent merges gate capacitors in parallel to achieve practical capacitance values that are not limited by parasitic effects. This combining approach allows the circuit to be manufactured with standard capacitor values while maintaining precise voltage distribution control across all transistors in the stack.
Solution Approach 2:
The patent introduces a new dimensional approach by organizing capacitors into parallel groups rather than using single capacitors for each transistor. This dimensional change in the capacitor network structure allows simultaneous achievement of precise voltage distribution and practical manufacturability.
3Reliability
If the stack height is increased to allow smaller transistors with smaller withstand voltage, then the transistor stress is reduced, but the gate capacitor capacitance values become impractically small
Solution Approach 1:
The patent combines gate capacitors in parallel for transistors at similar positions in the stack. This merging allows the use of taller stacks with smaller individual transistors that experience reduced stress, while the combined capacitor values remain at practical, manufacturable levels rather than becoming impractically small.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the practical implementation of higher stack heights while maintaining efficient voltage distribution and preventing transistor stress, enabling larger output power or using smaller transistors with smaller withstand voltage for a given output power, without sacrificing performance.
Implementation Method 1
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors
Data Source
AI summary
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.