RF Substrate Carbon Trapping Layer for Low Crosstalk
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Solution Overview
Problem
Existing silicon-on-insulator (SOI) substrates for radiofrequency integrated devices suffer from coupling losses and crosstalk due to electromagnetic field interactions with charge carriers in the substrate, leading to energy consumption and signal degradation.
Innovation Solution
A substrate with a very thin carbon layer (1-3 nm) acting as a trapping layer, sandwiched between a high-resistivity base substrate and an electrical insulating layer, effectively limits charge carrier interactions and prevents resistivity drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick trapping layer (several microns) of polycrystalline or amorphous semiconductor material is used to prevent charge carrier interactions, then RF performance is improved, but manufacturing cost increases and wafer deformation occurs
Solution Approach 1:
The patent changes the thickness parameter of the trapping layer from several microns to 1-3 nanometers, and changes the material from polycrystalline/amorphous semiconductor to amorphous carbon. This parameter change achieves the same charge trapping function while avoiding wafer deformation and reducing manufacturing cost.
Solution Approach 2:
The patent uses a thin amorphous carbon layer instead of thick polycrystalline or amorphous semiconductor layers. The carbon layer is simpler and cheaper to manufacture while still providing effective charge carrier trapping to prevent RF performance degradation.
2Reliability
If a thick trapping layer (several microns) is used to prevent charge carrier interactions, then RF performance is improved, but the layer becomes particularly rough and manufacturing becomes delicate
Solution Approach 1:
The patent changes the thickness parameter from several microns to 1-3 nanometers and uses amorphous carbon material, which inherently provides a smoother surface. This eliminates the roughness problem associated with thick polycrystalline or amorphous semiconductor layers while maintaining charge trapping effectiveness.
3Ease of manufacture
If no trapping layer is used in silicon-on-insulator substrates, then manufacturing is simpler, but coupling losses and crosstalk occur due to electromagnetic field interactions with charge carriers
Solution Approach 1:
The patent introduces a thin amorphous carbon layer as an intermediary between the insulating layer and the support substrate. This carbon layer acts as a mediator that traps charge carriers and prevents their interaction with electromagnetic fields, thereby reducing coupling losses while maintaining manufacturing simplicity.
4Reliability
If a carbon layer thicker than 5 nm is used, then charge trapping may be improved, but the simple and cost-effective advantage is lost
Solution Approach 1:
The patent optimizes the carbon layer thickness to 1-3 nanometers, which is sufficient to provide effective charge trapping. This optimized thickness maintains the manufacturing simplicity and cost-effectiveness advantages while achieving the required charge trapping effectiveness for RF performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thin carbon layer significantly improves RF performance by reducing coupling losses and crosstalk, achieving a 20 dBm gain in second harmonic distortion parameter compared to substrates without the carbon layer, while being simple and cost-effective to manufacture.
Implementation Method 1
The grain boundaries forming the polycrystal then constitute traps for the charge carriers, which can come from the trapping layer itself or from the underlying support.
Data Source
Figure 1~2
Figure 3a~3i
AI summary
The invention relates to a substrate (1) for applications in the fields of electronics and radiofrequency microelectronics, comprising a base substrate (3); a single carbon layer (2) that is disposed on and in direct contact with the base substrate (3), the carbon layer (2) having a thickness strictly between 1 nm and 5 nm; an electrically insulating layer (4) disposed on the carbon layer (2); and a layer (5) of devices disposed on the insulating layer (4). The invention also relates to a process for manufacturing said substrate.