Monolithic RF Circuit Substrate Parasitic Reduction
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Solution Overview
Problem
Monolithic RF circuits using bulk substrate technology face issues with substrate parasitics leading to degraded linearity and increased parasitic losses due to capacitive coupling and unwanted harmonics, which affect the performance of RF switches and passive components.
Innovation Solution
The method involves transferring layers to a front side glass substrate, removing the handle substrate, and forming a thermally conductive but electrically isolating layer on the back side of the semiconductor wafer to reduce substrate effects, thereby eliminating parasitic charges and improving RF signal linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high resistivity substrate is used to reduce parasitic losses, then substrate resistivity is improved, but fixed positive charges in dielectric layers induce inversion layer that decreases effective resistivity
Solution Approach 1:
The patent removes the high resistivity substrate entirely from the device structure. By extracting the substrate that causes parasitic losses and resistivity instability, the invention eliminates the root cause of the contradiction rather than attempting to manage its effects.
Solution Approach 2:
The patent introduces an electrically isolating layer as an intermediary between the device and the substrate. This mediator layer blocks the interaction between fixed positive charges in dielectric layers and the substrate, preventing inversion layer formation while maintaining mechanical support.
2Ease of manufacture
If bulk substrate technology is used for monolithic integration, then manufacturing simplicity is maintained, but substrate parasitics cause degraded linearity and voltage imbalance
Solution Approach 1:
The patent segments the device structure by separating the active device layer from the substrate through an electrically isolating layer. This segmentation eliminates parasitic coupling paths while maintaining the monolithic integrated structure, thereby preserving manufacturing simplicity while improving linearity.
Solution Approach 2:
The electrically isolating layer acts as a mediator between the substrate and the active devices, blocking parasitic substrate effects that degrade linearity and voltage balance, while allowing the devices to remain monolithically integrated on the substrate.
3Reliability
If dielectric layers with fixed positive charges are used on high resistivity substrate, then electrical insulation is provided, but inversion layer formation increases substrate conductivity
Solution Approach 1:
The patent introduces an electrically isolating layer as an intermediary between the substrate and the dielectric layers containing fixed positive charges. This mediator prevents the charges from inducing an inversion layer in the substrate, thereby maintaining both electrical insulation and high substrate resistivity.
Solution Approach 2:
The invention extracts or removes the problematic interaction between fixed positive charges and the substrate by placing an electrically isolating layer between them, eliminating the mechanism that converts insulation into conductivity enhancement.
4Speed
If capacitive coupling between metal layers and high resistivity substrate occurs, then signal transmission is enabled, but voltage dependent coupling degrades signal integrity
Solution Approach 1:
The electrically isolating layer serves as a mediator between metal layers and the substrate, providing a controlled electrical interface that enables signal transmission while eliminating voltage-dependent capacitive coupling effects that degrade signal integrity.
Solution Approach 2:
The patent changes the electrical parameters of the substrate interface by introducing the isolating layer, transforming the voltage-dependent capacitive coupling into a stable, controlled electrical interface with consistent signal transmission characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces substrate parasitics, enhancing RF signal linearity and reducing power loss by eliminating parasitic conduction layers and unwanted harmonics, allowing for increased cell density and improved device performance.
Implementation Method 1
forming a thermally conductive but electrically isolating layer on the back side of the semiconductor wafer
Implementation Method 2
forming a thermally conductive but electrically isolating layer on the back side of the semiconductor wafer to reduce substrate effects
Data Source
AI summary
A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.