RF Substrate Porous Interlayer for Stable Charge Trapping
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Solution Overview
Problem
Semiconductor-on-insulator substrates for RF applications face challenges in maintaining effective charge trapping layers, particularly at high frequencies, as heat treatments can reduce the effectiveness of polycrystalline silicon trapping layers due to grain size increase, leading to propagation losses and crosstalk.
Innovation Solution
Incorporating a porous layer between the support layer and the polycrystalline semiconductor trapping layer, which prevents recrystallization and maintains the structure of the trapping layer, and using a method involving porosification by hydrogen or rare gas implantation followed by thermal annealing to create closed pores for effective charge trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is applied to the substrate during manufacturing, then the insulating layer and support layer are properly formed, but the grain size in the polycrystalline silicon trapping layer increases which reduces its effectiveness
Solution Approach 1:
A porous interlayer is introduced between the support layer and the polycrystalline silicon trapping layer. This interlayer acts as a barrier that prevents the propagation of recrystallization from the support layer to the trapping layer during high-temperature heat treatments, thereby protecting the grain structure and trapping effectiveness of the polycrystalline silicon layer
Solution Approach 2:
The porous interlayer is specifically positioned only where needed - between the support layer and the trapping layer - to provide localized protection against recrystallization. This allows the rest of the substrate to undergo necessary heat treatments without compromising the trapping layer's grain structure
2Reliability
If an interlayer is added between the support layer and trapping layer to prevent recrystallization, then the trapping layer structure is maintained, but the device complexity and manufacturing cost increase due to additional polishing steps
Solution Approach 1:
The interlayer is designed with a porous structure that can be formed through controlled porosity generation in the support layer. This porous structure inherently provides the necessary barrier function while potentially reducing the need for additional processing steps compared to dense interlayer materials that would require CMP polishing
3Reliability
If the polycrystalline silicon trapping layer is used to trap charges, then propagation losses and crosstalk are reduced, but the layer undergoes harmful modifications during high-temperature manufacturing steps
Solution Approach 1:
The porous interlayer is placed in advance between the support layer and the trapping layer to provide protective cushioning against the harmful effects of high-temperature heat treatments. This pre-positioned barrier prevents thermal damage and unwanted recrystallization before they can affect the trapping layer during subsequent manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The porous layer effectively prevents recrystallization and enhances charge trapping capabilities, reducing parasitic conduction and propagation losses, thereby improving the performance of RF substrates at high frequencies.
Implementation Method 1
Such a porous layer can prevent the propagation of a recrystallization front from the support layer to the insulating layer
Implementation Method 2
a charge trapping layer, said trapping layer comprising a layer of polycrystalline semiconductor material located between said insulating layer and said support layer
Implementation Method 3
using a method involving porosification by hydrogen or rare gas implantation followed by thermal annealing
Implementation Method 4
porosification by hydrogen or rare gas implantation followed by thermal annealing to create closed pores
Data Source
Figure 1~2B
Figure 3A~3F
Figure 4A~4C
AI summary
Fabrication of a semiconductor or piezoelectric substrate on insulator for RF applications equipped with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material (figure 1).