RF On-Insulator Substrate with Porous Layer for Trap-Rich Stability
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Solution Overview
Problem
Semiconductor-on-insulator substrates for RF applications face challenges in maintaining the efficiency of trap-rich layers due to heat treatment, which can cause grain size increase and reduce their effectiveness, and existing methods like CMP polishing are costly.
Innovation Solution
Incorporating a porous layer with closed pores between the support and trap-rich layers to prevent recrystallization and enhance the trap-rich layer's efficiency, using porosification techniques like hydrogen or rare gas implantation followed by thermal annealing to form a porous surface region, and depositing a polycrystalline semiconductor material on this layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If heat treatment is applied during substrate manufacture, then processing can be completed, but the grain size in the trap-rich layer increases which reduces its efficiency
Solution Approach 1:
An interlayer is introduced between the support layer and the trap-rich layer to act as a barrier that prevents crystal structure transmission during heat treatment. This intermediary layer blocks the recrystallization process from affecting the trap-rich layer while allowing the heat treatment to proceed for completing the substrate manufacturing process.
Solution Approach 2:
The interlayer is designed with a porous structure consisting of a solid skeleton and distributed pores. This porous configuration provides effective barrier properties against crystal transmission while maintaining structural integrity during high-temperature processing, preventing grain growth in the trap-rich layer.
2Reliability
If an interlayer is integrated between the support layer and trap-rich layer, then recrystallization is prevented, but manufacturing complexity increases
Solution Approach 1:
The interlayer utilizes a porous structure with a solid skeleton and distributed pores that can be formed through standard semiconductor processing techniques. This approach prevents recrystallization while maintaining compatibility with existing manufacturing processes, minimizing the increase in manufacturing complexity.
3Manufacturing precision
If CMP polishing is used to complete the substrate, then surface flatness is achieved, but manufacturing cost increases
Solution Approach 1:
The porous interlayer serves as a sacrificial or functional layer that can be removed or retained to achieve the desired surface characteristics. By using this interlayer as a mediator, the need for costly CMP polishing is eliminated while still achieving the necessary surface flatness and structural integrity for RF applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The porous layer effectively prevents recrystallization and maintains the trap-rich layer's efficiency, reducing propagation losses and crosstalk while avoiding costly polishing steps, thus improving the substrate's performance for RF applications.
Implementation Method 1
a porous layer provided with a lower face in contact with said support layer, said porous layer being formed of a solid skeleton and a distribution of pores that are empty and/or gas filled
Implementation Method 2
using porosification techniques like hydrogen or rare gas implantation followed by thermal annealing to form a porous surface region
Implementation Method 3
followed by thermal annealing to form a porous surface region
Implementation Method 4
depositing a polycrystalline semiconductor material on this layer
Data Source
AI summary
Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.