Engineered RF Substrate Structure for GaN Thermal Mismatch

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High frequency, high performance RF devices face issues due to lattice mismatch and thermal expansion coefficient disparities between GaN and carrier substrates, leading to defects, dislocations, and increased manufacturing costs.

Innovation Solution

The use of an engineered substrate with a polycrystalline ceramic core and interlayer structure, including silicon oxide and silicon nitride layers, coupled with a single crystalline silicon layer, to match thermal expansion coefficients and reduce thermal resistance, inductance, and impedance, enabling high-frequency operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If GaN is deposited on a carrier substrate with a different lattice structure, then RF devices can be fabricated, but defects and dislocations are created due to lattice mismatch

Engineering Contradiction:
ImproveRF device fabricationVSAvoiddefects and dislocations
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A multi-layer buffer structure is introduced between the GaN layer and the carrier substrate. This buffer structure includes layers with gradually changing lattice constants that serve as an intermediary, reducing the abrupt lattice mismatch and minimizing defects and dislocations in the GaN layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The lattice constant parameter is gradually changed through the buffer layers, transitioning from the carrier substrate's lattice constant to the GaN layer's lattice constant. This gradual parameter change reduces stress and defect formation compared to direct deposition on mismatched substrates.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If thermal processing is performed on GaN layers with carrier substrates, then epitaxial growth can be achieved, but cracking and delamination occur due to different coefficients of thermal expansion

Engineering Contradiction:
Improveepitaxial growthVSAvoidcracking and delamination
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The buffer structure is specifically designed with materials and thicknesses that account for thermal expansion differences. The multi-layer structure distributes thermal stress across multiple interfaces, preventing catastrophic cracking and delamination during epitaxial growth and subsequent thermal processing.

Inventive Principle:
Principle #37Thermal expansion

Solution Approach 2:

A composite buffer structure comprising multiple materials with different thermal expansion coefficients is used. This composite structure gradually transitions the thermal expansion properties from the carrier substrate to the GaN layer, reducing thermal stress and improving reliability during thermal processing.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If carrier substrates are used for GaN fabrication, then RF devices can be produced, but substrate bowing and breaking occur during thermal processing

Engineering Contradiction:
ImproveRF device productionVSAvoidsubstrate integrity
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The buffer structure compensates for thermal expansion mismatches that cause substrate bowing. By distributing thermal stress across multiple layers with graded thermal expansion properties, the structure prevents excessive bowing and subsequent substrate breaking during thermal processing.

Inventive Principle:
Principle #37Thermal expansion

4Ease of manufacture

If different coefficients of thermal expansion between GaN and carrier substrate are accommodated, then thermal stress is reduced, but substrate wafer size is restricted and manufacturing cost increases

Engineering Contradiction:
Improvemanufacturing costVSAvoidsubstrate structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The buffer structure is segmented into multiple thin layers rather than a single thick layer. This segmentation allows better stress distribution and thermal management while maintaining a relatively simple overall structure that can be integrated into standard fabrication processes, avoiding excessive complexity and cost.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in high-frequency RF devices with reduced defects, lower manufacturing costs, and improved thermal performance, allowing for larger wafer sizes and more complex circuitry.

Implementation Method 1

The GaN layers and carrier substrate may have different coefficients of thermal expansion (CTEs). Thermal processing (e.g., GaN epitaxial growth) can crack or delaminate the GaN, or bow and, in some cases, break the carrier substrate.

Methodology Applied
Scientific EffectThermal expansion coefficient matching: Thermal Expansion

Implementation Method 2

epitaxial layers, such as gallium nitride (GaN), may be formed by a heteroepitaxial (epi) growth process that involves depositing GaN on a semiconductor carrier substrate

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentEP3586355B1RF device integrated on an engineered substrate
Publication Date: 2026.04.01 QROMIS INC
  • EP3586355B1 patent drawingFigure 1
  • EP3586355B1 patent drawingFigure 2
  • EP3586355B1 patent drawingFigure 3A

AI summary

A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.