RF Switch Back-Gate Capacitor Layout for Soft Compression Control
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Solution Overview
Problem
In RF switch designs with stacked FETs, increasing the number of transistors to improve RF voltage handling leads to increased parasitic capacitance, causing deleterious soft compression and on resistance modulation, which complicates performance optimization.
Innovation Solution
Incorporating secondary gate-connected compensation capacitors in the RF switch circuit, which are preselected to have different capacitances to limit parasitic capacitance between secondary gates and the semiconductor substrate, allowing for more transistors to be added without significant increases in on resistance modulation or soft compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of stacked FETs is increased to improve RF voltage handling, then RF voltage handling capability is improved, but parasitic capacitance to the semiconductor substrate increases causing on resistance modulation and soft compression
Solution Approach 1:
Compensation capacitors are introduced as intermediary elements connected between the secondary gates and ground. These capacitors serve as mediators that counterbalance the parasitic capacitance effects by providing an opposing capacitive path, thereby reducing the net parasitic capacitance impact on the RF switch performance while allowing more FETs to be stacked for improved voltage handling
Solution Approach 2:
The invention changes the electrical parameters of the system by introducing compensation capacitors with specific capacitance values that are designed to offset the parasitic capacitance. By adjusting the compensation capacitor values, the overall parasitic capacitance effect can be minimized, allowing the stacked FET configuration to maintain stable on-resistance characteristics even with increased FET count
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the increase in the number of transistors to meet RF voltage handling requirements without substantial increases in on resistance modulation or soft compression, thereby improving performance without compromising other parameters.
Implementation Method 1
parasitic capacitance to the semiconductor substrate increases with each additional back gate of each additional FET. The increase in parasitic capacitance to the semiconductor substrate modulates the on resistance (Ron) and introduces deleterious soft compression.
Implementation Method 2
The structure comprises capacitors. Each capacitor is electrically connected to the second node and to the secondary gate of one of the transistors.
Data Source
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AI summary
A disclosed structure (e.g., a switch circuit) includes multiple transistors (e.g., on triple wells) connected in series between a first and second nodes. Each transistor can include a primary gate (e.g., a front gate) for controlling the ON/OFF state of the transistor and a secondary gate (e.g., a back gate) for adjusting the VT of the transistor. The switch circuit further includes multiple capacitors (e.g., APMOM capacitors on triple wells), each connected to the second node and to the secondary gate of a corresponding one of the transistors. In advanced semiconductor-on-insulator processing technology platforms, each secondary gate includes a well region within a semiconductor substrate and a corresponding section of an insulator layer, which is on the semiconductor substrate and adjacent to an active device region for the transistor. The capacitors are preselected during design and different capacitances for limiting parasitic secondary gate-to-substrate coupling. Also disclosed are associated methods.