RF Switch Bias Bypass Circuit for Faster High-Q Switching
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Solution Overview
Problem
Radio Frequency (RF) switches face a design trade-off between achieving fast response times and high power handling while maintaining a high Quality Factor (Q) in the off state, as large bias resistor values are required for high Q but lead to long switching times due to large Resistor-Capacitor (RC) time constants.
Innovation Solution
The implementation of auxiliary shorting switches using local bias networks that bypass gate and drain/source bias resistors during turn-on, allowing for accelerated switching without additional bias resistor networks, and a rectification circuit to reduce body current during high-VDS conditions, enhancing power handling and Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large bias resistor values are used to achieve high Q factor in the off state, then the Quality Factor is improved, but the switching time increases due to large RC time constants
Solution Approach 1:
The patent applies preliminary action by using auxiliary switches to pre-charge or pre-discharge the gate nodes before the main switching action. This prepares the circuit state in advance, reducing the RC time constant effect during the actual switching event and enabling faster transition times while maintaining the high Q factor achieved through large bias resistors.
Solution Approach 2:
The patent introduces auxiliary switches as intermediary elements that mediate between the control signal and the main switching devices. These auxiliary switches actively manage the charging/discharging of gate capacitances, decoupling the switching speed from the bias resistor values and allowing independent optimization of both Q factor and switching time.
2Speed
If low bias resistor values are used to reduce RC time constants and improve switching speed, then the switching time is reduced, but the Quality Factor decreases
Solution Approach 1:
The auxiliary switches perform preliminary charging or discharging of gate nodes, allowing the use of lower bias resistor values for faster switching without sacrificing Q factor. The preliminary action compensates for the reduced resistance effect, maintaining both speed and quality factor performance.
Solution Approach 2:
The patent changes the effective resistance parameter dynamically during switching transitions. By using auxiliary switches to temporarily alter the circuit configuration, the effective resistance seen by the gate capacitance is reduced during switching events, enabling fast switching while the bias resistors maintain their high Q factor characteristics during steady state.
3Loss of time
If additional bias resistor networks are added to accelerate switching, then the switching time is reduced, but the device complexity increases
Solution Approach 1:
The auxiliary switches are designed to serve multiple functions: they accelerate switching by managing gate capacitances, and they can also contribute to the biasing network. This multi-functionality reduces the need for separate dedicated acceleration circuits, thereby limiting the increase in device complexity while achieving faster switching times.
Solution Approach 2:
The patent merges the switching acceleration function with the existing bias resistor network and auxiliary switch structures. By combining these functions into a unified circuit architecture, the patent avoids the complexity that would result from adding completely separate acceleration circuits, achieving fast switching with minimal complexity increase.
Data Source
AI summary
A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.