RF Switch Bias Circuit With Gate-Gate Resistors for Lower Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
RF switches experience significant dissipative losses and reduced quality factor due to high impedance in the OFF state, leading to mismatch and resonant circuit degradation.
Innovation Solution
Implementing gate, drain-source, and body resistances to bias transistors in a switch stack, optimizing series and shunt arms, and using gate-gate resistors to minimize resistance roll-off and dissipative losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high impedance is used in the OFF state of RF switches, then switching isolation is improved, but dissipative losses increase and quality factor decreases
Solution Approach 1:
The patent changes the electrical parameters of the switch transistors by introducing gate resistors (Rg), drain-source resistors (Rds), and body resistors (Rb) to modify the impedance characteristics in the OFF state. This allows achieving both high isolation and low dissipative losses by optimizing the resistance values to minimize the Q-factor degradation while maintaining sufficient off-state impedance.
Solution Approach 2:
The patent introduces resistor elements as intermediary components between the transistor terminals. These resistors act as mediators to control the impedance in the OFF state, providing a path to reduce dissipative losses while maintaining the necessary isolation characteristics. The gate-gate resistors specifically serve as intermediaries to minimize resistance roll-off effects.
2Reliability
If high impedance is used in the OFF state of RF switches, then switching isolation is improved, but quality factor decreases
Solution Approach 1:
The patent modifies the electrical parameters by adding resistance elements with specific values to control the quality factor. The gate resistors, drain-source resistors, and body resistors are designed with optimized values to minimize Q-factor degradation while maintaining high isolation, effectively decoupling these two performance parameters.
Solution Approach 2:
The patent applies different resistance values and configurations to different parts of the switch circuit (gate, drain-source, body terminals) to optimize local impedance characteristics. This local quality adjustment allows each terminal to contribute differently to the overall performance, with gate-gate resistors specifically targeted to minimize resistance roll-off in critical regions.
3Loss of energy
If gate-gate resistors are added to minimize resistance roll-off, then dissipative losses are reduced, but device complexity increases
Solution Approach 1:
The patent merges the biasing function and the resistance roll-off minimization function into a single gate-gate resistor component. This resistor simultaneously provides the necessary bias conditions for the transistor while also minimizing the resistance roll-off effect, thereby reducing dissipative losses without requiring separate biasing circuits or additional components.
Solution Approach 2:
The gate-gate resistors are designed to serve multiple functions: providing DC bias conditions for the transistor, minimizing resistance roll-off at high frequencies, and contributing to the overall impedance control in the OFF state. This multi-functionality reduces the need for separate components and simplifies the overall circuit design despite the added functionality.
Data Source
AI summary
In some embodiments, a switching circuit can include a first node and a second node, and a plurality of transistors implemented in a stack configuration between the first node and the second node, with each transistor having a source, a drain and a gate, and the transistors being configured to be in an ON state or an OFF state to respectively allow or inhibit passage of a signal between the first and second nodes. The switching circuit can further include a bias circuit configured to bias the transistors from a bias node. The bias circuit can include a gate-gate resistor that couples each pair of neighboring transistors of the plurality of transistors, and a feed node coupled to the bias node, with the feed node being connected directly to the gate of a selected transistor of the plurality of transistors.