RF Switch Biasing Topology Without NVGs or Cross-Bias Capacitors
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Solution Overview
Problem
Existing RF switching circuits face challenges in minimizing on-resistance and off-capacitance while maintaining good RF and electrostatic discharge performance, often requiring Negative Voltage Generators (NVGs) or cross-bias capacitors, which can increase controller die size and standby current or degrade RF performance.
Innovation Solution
The proposed solution involves a switching circuit topology using multiple series and shunt Field-Effect Transistors (FETs) with specific gate and source voltage configurations to create a back-to-back diode configuration, eliminating the need for NVGs and cross-bias capacitors, and achieving low voltage clipping and compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Negative Voltage Generators (NVGs) or cross-bias capacitors are used to minimize off-capacitance and non-linearity, then switch performance is improved, but controller die size and standby current increase
Solution Approach 1:
The patent extracts and eliminates the NVG and cross-bias capacitor components from the switching circuit. By using a simplified biasing topology with separate gate voltage nodes, the circuit achieves the same switch performance improvement without requiring the additional NVG or capacitor components, thus reducing controller die size.
Solution Approach 2:
The patent introduces intermediate gate voltage nodes (first gate voltage node and second gate voltage node) that serve as mediators to provide the necessary voltage differences for switch control. These intermediate nodes replace the need for NVGs and cross-bias capacitors, achieving the same effect through a different voltage distribution mechanism.
2Reliability
If Negative Voltage Generators (NVGs) or cross-bias capacitors are used to minimize off-capacitance and non-linearity, then switch performance is improved, but standby current increases
Solution Approach 1:
The patent removes the NVG and cross-bias capacitor from the circuit, eliminating the standby current consumption associated with these components. The simplified topology maintains switch performance through alternative voltage node configuration without the energy overhead of NVGs or capacitors.
Solution Approach 2:
The gate voltage nodes are configured to automatically provide the necessary voltage differences for switch control without requiring external NVGs or capacitors. The circuit self-regulates the gate voltages through its inherent topology, eliminating the need for additional energy-consuming components.
3Reliability
If multiple FETs are used in series configuration to minimize on-resistance, then RF performance is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple FETs into series configurations within the switching circuit. By combining FETs in series with properly configured gate voltage nodes, the circuit achieves reduced on-resistance and improved RF performance while maintaining a manageable topology through systematic voltage node assignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This topology provides efficient RF and electrostatic discharge performance without the need for NVGs or cross-bias capacitors, reducing controller die size and standby current, and is compatible with Silicon-on-Insulator processes, including CMOS and Bipolar CMOS processes.
Implementation Method 1
a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET
Data Source
AI summary
A switching circuit comprises a first series switch coupled to a first output port, the first series switch including a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, a second series switch coupled to a second output port, and coupling circuitry configured to couple a gate of the fifth FET and a gate of the sixth FET to a first node, a source of the fifth FET and a drain of the sixth FET to a second node, a source of the first FET and a drain of the second FET to a third node, a gate of the first FET and a drain of the fifth FET to a fourth node, a gate of the second FET and a source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage that is different than the first gate voltage.